1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file When allowed by the instruction, replace a dead definition of a GPR 9 /// with the zero register. This makes the code a bit friendlier towards the 10 /// hardware's register renamer. 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64.h" 14 #include "AArch64RegisterInfo.h" 15 #include "AArch64Subtarget.h" 16 #include "llvm/ADT/Statistic.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineFunctionPass.h" 19 #include "llvm/CodeGen/MachineInstr.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/TargetInstrInfo.h" 22 #include "llvm/CodeGen/TargetSubtargetInfo.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/raw_ostream.h" 25 using namespace llvm; 26 27 #define DEBUG_TYPE "aarch64-dead-defs" 28 29 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced"); 30 31 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions" 32 33 namespace { 34 class AArch64DeadRegisterDefinitions : public MachineFunctionPass { 35 private: 36 const TargetRegisterInfo *TRI; 37 const MachineRegisterInfo *MRI; 38 const TargetInstrInfo *TII; 39 bool Changed; 40 void processMachineBasicBlock(MachineBasicBlock &MBB); 41 public: 42 static char ID; // Pass identification, replacement for typeid. 43 AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) { 44 initializeAArch64DeadRegisterDefinitionsPass( 45 *PassRegistry::getPassRegistry()); 46 } 47 48 bool runOnMachineFunction(MachineFunction &F) override; 49 50 StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; } 51 52 void getAnalysisUsage(AnalysisUsage &AU) const override { 53 AU.setPreservesCFG(); 54 MachineFunctionPass::getAnalysisUsage(AU); 55 } 56 }; 57 char AArch64DeadRegisterDefinitions::ID = 0; 58 } // end anonymous namespace 59 60 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs", 61 AARCH64_DEAD_REG_DEF_NAME, false, false) 62 63 static bool usesFrameIndex(const MachineInstr &MI) { 64 for (const MachineOperand &MO : MI.uses()) 65 if (MO.isFI()) 66 return true; 67 return false; 68 } 69 70 // Instructions that lose their 'read' operation for a subesquent fence acquire 71 // (DMB LD) once the zero register is used. 72 // 73 // WARNING: The aquire variants of the instructions are also affected, but they 74 // are split out into `atomicBarrierDroppedOnZero()` to support annotations on 75 // assembly. 76 static bool atomicReadDroppedOnZero(unsigned Opcode) { 77 switch (Opcode) { 78 case AArch64::LDADDB: case AArch64::LDADDH: 79 case AArch64::LDADDW: case AArch64::LDADDX: 80 case AArch64::LDADDLB: case AArch64::LDADDLH: 81 case AArch64::LDADDLW: case AArch64::LDADDLX: 82 case AArch64::LDCLRB: case AArch64::LDCLRH: 83 case AArch64::LDCLRW: case AArch64::LDCLRX: 84 case AArch64::LDCLRLB: case AArch64::LDCLRLH: 85 case AArch64::LDCLRLW: case AArch64::LDCLRLX: 86 case AArch64::LDEORB: case AArch64::LDEORH: 87 case AArch64::LDEORW: case AArch64::LDEORX: 88 case AArch64::LDEORLB: case AArch64::LDEORLH: 89 case AArch64::LDEORLW: case AArch64::LDEORLX: 90 case AArch64::LDSETB: case AArch64::LDSETH: 91 case AArch64::LDSETW: case AArch64::LDSETX: 92 case AArch64::LDSETLB: case AArch64::LDSETLH: 93 case AArch64::LDSETLW: case AArch64::LDSETLX: 94 case AArch64::LDSMAXB: case AArch64::LDSMAXH: 95 case AArch64::LDSMAXW: case AArch64::LDSMAXX: 96 case AArch64::LDSMAXLB: case AArch64::LDSMAXLH: 97 case AArch64::LDSMAXLW: case AArch64::LDSMAXLX: 98 case AArch64::LDSMINB: case AArch64::LDSMINH: 99 case AArch64::LDSMINW: case AArch64::LDSMINX: 100 case AArch64::LDSMINLB: case AArch64::LDSMINLH: 101 case AArch64::LDSMINLW: case AArch64::LDSMINLX: 102 case AArch64::LDUMAXB: case AArch64::LDUMAXH: 103 case AArch64::LDUMAXW: case AArch64::LDUMAXX: 104 case AArch64::LDUMAXLB: case AArch64::LDUMAXLH: 105 case AArch64::LDUMAXLW: case AArch64::LDUMAXLX: 106 case AArch64::LDUMINB: case AArch64::LDUMINH: 107 case AArch64::LDUMINW: case AArch64::LDUMINX: 108 case AArch64::LDUMINLB: case AArch64::LDUMINLH: 109 case AArch64::LDUMINLW: case AArch64::LDUMINLX: 110 case AArch64::SWPB: case AArch64::SWPH: 111 case AArch64::SWPW: case AArch64::SWPX: 112 case AArch64::SWPLB: case AArch64::SWPLH: 113 case AArch64::SWPLW: case AArch64::SWPLX: 114 return true; 115 } 116 return false; 117 } 118 119 void AArch64DeadRegisterDefinitions::processMachineBasicBlock( 120 MachineBasicBlock &MBB) { 121 const MachineFunction &MF = *MBB.getParent(); 122 for (MachineInstr &MI : MBB) { 123 if (usesFrameIndex(MI)) { 124 // We need to skip this instruction because while it appears to have a 125 // dead def it uses a frame index which might expand into a multi 126 // instruction sequence during EPI. 127 LLVM_DEBUG(dbgs() << " Ignoring, operand is frame index\n"); 128 continue; 129 } 130 if (MI.definesRegister(AArch64::XZR, /*TRI=*/nullptr) || 131 MI.definesRegister(AArch64::WZR, /*TRI=*/nullptr)) { 132 // It is not allowed to write to the same register (not even the zero 133 // register) twice in a single instruction. 134 LLVM_DEBUG( 135 dbgs() 136 << " Ignoring, XZR or WZR already used by the instruction\n"); 137 continue; 138 } 139 140 if (atomicBarrierDroppedOnZero(MI.getOpcode()) || atomicReadDroppedOnZero(MI.getOpcode())) { 141 LLVM_DEBUG(dbgs() << " Ignoring, semantics change with xzr/wzr.\n"); 142 continue; 143 } 144 145 const MCInstrDesc &Desc = MI.getDesc(); 146 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { 147 MachineOperand &MO = MI.getOperand(I); 148 if (!MO.isReg() || !MO.isDef()) 149 continue; 150 // We should not have any relevant physreg defs that are replacable by 151 // zero before register allocation. So we just check for dead vreg defs. 152 Register Reg = MO.getReg(); 153 if (!Reg.isVirtual() || (!MO.isDead() && !MRI->use_nodbg_empty(Reg))) 154 continue; 155 assert(!MO.isImplicit() && "Unexpected implicit def!"); 156 LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; 157 MI.print(dbgs())); 158 // Be careful not to change the register if it's a tied operand. 159 if (MI.isRegTiedToUseOperand(I)) { 160 LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); 161 continue; 162 } 163 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); 164 unsigned NewReg; 165 if (RC == nullptr) { 166 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); 167 continue; 168 } else if (RC->contains(AArch64::WZR)) 169 NewReg = AArch64::WZR; 170 else if (RC->contains(AArch64::XZR)) 171 NewReg = AArch64::XZR; 172 else { 173 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); 174 continue; 175 } 176 LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n "); 177 MO.setReg(NewReg); 178 MO.setIsDead(); 179 LLVM_DEBUG(MI.print(dbgs())); 180 ++NumDeadDefsReplaced; 181 Changed = true; 182 // Only replace one dead register, see check for zero register above. 183 break; 184 } 185 } 186 } 187 188 // Scan the function for instructions that have a dead definition of a 189 // register. Replace that register with the zero register when possible. 190 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { 191 if (skipFunction(MF.getFunction())) 192 return false; 193 194 TRI = MF.getSubtarget().getRegisterInfo(); 195 TII = MF.getSubtarget().getInstrInfo(); 196 MRI = &MF.getRegInfo(); 197 LLVM_DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); 198 Changed = false; 199 for (auto &MBB : MF) 200 processMachineBasicBlock(MBB); 201 return Changed; 202 } 203 204 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() { 205 return new AArch64DeadRegisterDefinitions(); 206 } 207