1 /* $NetBSD: amdgpu_arcturus_ppt.c,v 1.4 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_arcturus_ppt.c,v 1.4 2021/12/19 12:21:29 riastradh Exp $");
28
29 #include "pp_debug.h"
30 #include <linux/firmware.h>
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "smu_internal.h"
34 #include "atomfirmware.h"
35 #include "amdgpu_atomfirmware.h"
36 #include "smu_v11_0.h"
37 #include "smu11_driver_if_arcturus.h"
38 #include "soc15_common.h"
39 #include "atom.h"
40 #include "power_state.h"
41 #include "arcturus_ppt.h"
42 #include "smu_v11_0_pptable.h"
43 #include "arcturus_ppsmc.h"
44 #include "nbio/nbio_7_4_sh_mask.h"
45 #include "amdgpu_xgmi.h"
46 #include <linux/i2c.h>
47 #include <linux/pci.h>
48 #include "amdgpu_ras.h"
49
50 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
51
52 #define CTF_OFFSET_EDGE 5
53 #define CTF_OFFSET_HOTSPOT 5
54 #define CTF_OFFSET_HBM 5
55
56 #define MSG_MAP(msg, index) \
57 [SMU_MSG_##msg] = {1, (index)}
58 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
59 [smu_feature] = {1, (arcturus_feature)}
60
61 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
62 #define SMU_FEATURES_LOW_SHIFT 0
63 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
64 #define SMU_FEATURES_HIGH_SHIFT 32
65
66 #define SMC_DPM_FEATURE ( \
67 FEATURE_DPM_PREFETCHER_MASK | \
68 FEATURE_DPM_GFXCLK_MASK | \
69 FEATURE_DPM_UCLK_MASK | \
70 FEATURE_DPM_SOCCLK_MASK | \
71 FEATURE_DPM_MP0CLK_MASK | \
72 FEATURE_DPM_FCLK_MASK | \
73 FEATURE_DPM_XGMI_MASK)
74
75 /* possible frequency drift (1Mhz) */
76 #define EPSILON 1
77
78 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
79 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
80 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
81 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
82 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
83 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
84 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
85 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
86 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
87 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
88 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
89 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
90 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
91 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
92 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
93 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
94 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
95 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
96 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
97 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
98 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
99 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
100 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
101 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
102 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
103 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
104 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
105 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
106 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
107 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
108 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
109 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
110 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
111 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
112 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
113 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType),
114 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm),
115 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive),
116 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
117 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
118 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0),
119 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0),
120 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1),
121 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1),
122 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
123 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
124 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
125 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset),
126 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc),
127 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc),
128 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
129 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
130 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
131 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
132 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest),
133 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode),
134 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable),
135 };
136
137 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
138 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
139 CLK_MAP(SCLK, PPCLK_GFXCLK),
140 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
141 CLK_MAP(FCLK, PPCLK_FCLK),
142 CLK_MAP(UCLK, PPCLK_UCLK),
143 CLK_MAP(MCLK, PPCLK_UCLK),
144 CLK_MAP(DCLK, PPCLK_DCLK),
145 CLK_MAP(VCLK, PPCLK_VCLK),
146 };
147
148 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
149 FEA_MAP(DPM_PREFETCHER),
150 FEA_MAP(DPM_GFXCLK),
151 FEA_MAP(DPM_UCLK),
152 FEA_MAP(DPM_SOCCLK),
153 FEA_MAP(DPM_FCLK),
154 FEA_MAP(DPM_MP0CLK),
155 ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
156 FEA_MAP(DS_GFXCLK),
157 FEA_MAP(DS_SOCCLK),
158 FEA_MAP(DS_LCLK),
159 FEA_MAP(DS_FCLK),
160 FEA_MAP(DS_UCLK),
161 FEA_MAP(GFX_ULV),
162 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
163 FEA_MAP(RSMU_SMN_CG),
164 FEA_MAP(WAFL_CG),
165 FEA_MAP(PPT),
166 FEA_MAP(TDC),
167 FEA_MAP(APCC_PLUS),
168 FEA_MAP(VR0HOT),
169 FEA_MAP(VR1HOT),
170 FEA_MAP(FW_CTF),
171 FEA_MAP(FAN_CONTROL),
172 FEA_MAP(THERMAL),
173 FEA_MAP(OUT_OF_BAND_MONITOR),
174 FEA_MAP(TEMP_DEPENDENT_VMIN),
175 };
176
177 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
178 TAB_MAP(PPTABLE),
179 TAB_MAP(AVFS),
180 TAB_MAP(AVFS_PSM_DEBUG),
181 TAB_MAP(AVFS_FUSE_OVERRIDE),
182 TAB_MAP(PMSTATUSLOG),
183 TAB_MAP(SMU_METRICS),
184 TAB_MAP(DRIVER_SMU_CONFIG),
185 TAB_MAP(OVERDRIVE),
186 TAB_MAP(I2C_COMMANDS),
187 TAB_MAP(ACTIVITY_MONITOR_COEFF),
188 };
189
190 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
191 PWR_MAP(AC),
192 PWR_MAP(DC),
193 };
194
195 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
196 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
197 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
198 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
199 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
200 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
201 };
202
arcturus_get_smu_msg_index(struct smu_context * smc,uint32_t index)203 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
204 {
205 struct smu_11_0_cmn2aisc_mapping mapping;
206
207 if (index >= SMU_MSG_MAX_COUNT)
208 return -EINVAL;
209
210 mapping = arcturus_message_map[index];
211 if (!(mapping.valid_mapping))
212 return -EINVAL;
213
214 return mapping.map_to;
215 }
216
arcturus_get_smu_clk_index(struct smu_context * smc,uint32_t index)217 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
218 {
219 struct smu_11_0_cmn2aisc_mapping mapping;
220
221 if (index >= SMU_CLK_COUNT)
222 return -EINVAL;
223
224 mapping = arcturus_clk_map[index];
225 if (!(mapping.valid_mapping)) {
226 pr_warn("Unsupported SMU clk: %d\n", index);
227 return -EINVAL;
228 }
229
230 return mapping.map_to;
231 }
232
arcturus_get_smu_feature_index(struct smu_context * smc,uint32_t index)233 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
234 {
235 struct smu_11_0_cmn2aisc_mapping mapping;
236
237 if (index >= SMU_FEATURE_COUNT)
238 return -EINVAL;
239
240 mapping = arcturus_feature_mask_map[index];
241 if (!(mapping.valid_mapping)) {
242 return -EINVAL;
243 }
244
245 return mapping.map_to;
246 }
247
arcturus_get_smu_table_index(struct smu_context * smc,uint32_t index)248 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
249 {
250 struct smu_11_0_cmn2aisc_mapping mapping;
251
252 if (index >= SMU_TABLE_COUNT)
253 return -EINVAL;
254
255 mapping = arcturus_table_map[index];
256 if (!(mapping.valid_mapping)) {
257 pr_warn("Unsupported SMU table: %d\n", index);
258 return -EINVAL;
259 }
260
261 return mapping.map_to;
262 }
263
arcturus_get_pwr_src_index(struct smu_context * smc,uint32_t index)264 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
265 {
266 struct smu_11_0_cmn2aisc_mapping mapping;
267
268 if (index >= SMU_POWER_SOURCE_COUNT)
269 return -EINVAL;
270
271 mapping = arcturus_pwr_src_map[index];
272 if (!(mapping.valid_mapping)) {
273 pr_warn("Unsupported SMU power source: %d\n", index);
274 return -EINVAL;
275 }
276
277 return mapping.map_to;
278 }
279
280
arcturus_get_workload_type(struct smu_context * smu,enum PP_SMC_POWER_PROFILE profile)281 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
282 {
283 struct smu_11_0_cmn2aisc_mapping mapping;
284
285 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
286 return -EINVAL;
287
288 mapping = arcturus_workload_map[profile];
289 if (!(mapping.valid_mapping))
290 return -EINVAL;
291
292 return mapping.map_to;
293 }
294
arcturus_tables_init(struct smu_context * smu,struct smu_table * tables)295 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
296 {
297 struct smu_table_context *smu_table = &smu->smu_table;
298
299 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
300 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
301
302 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
303 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
304
305 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
306 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
307
308 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
309 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
310
311 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
312 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
313 AMDGPU_GEM_DOMAIN_VRAM);
314
315 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
316 if (!smu_table->metrics_table)
317 return -ENOMEM;
318 smu_table->metrics_time = 0;
319
320 return 0;
321 }
322
arcturus_allocate_dpm_context(struct smu_context * smu)323 static int arcturus_allocate_dpm_context(struct smu_context *smu)
324 {
325 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
326
327 if (smu_dpm->dpm_context)
328 return -EINVAL;
329
330 smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
331 GFP_KERNEL);
332 if (!smu_dpm->dpm_context)
333 return -ENOMEM;
334
335 if (smu_dpm->golden_dpm_context)
336 return -EINVAL;
337
338 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
339 GFP_KERNEL);
340 if (!smu_dpm->golden_dpm_context)
341 return -ENOMEM;
342
343 smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
344
345 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
346 GFP_KERNEL);
347 if (!smu_dpm->dpm_current_power_state)
348 return -ENOMEM;
349
350 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
351 GFP_KERNEL);
352 if (!smu_dpm->dpm_request_power_state)
353 return -ENOMEM;
354
355 return 0;
356 }
357
358 static int
arcturus_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)359 arcturus_get_allowed_feature_mask(struct smu_context *smu,
360 uint32_t *feature_mask, uint32_t num)
361 {
362 if (num > 2)
363 return -EINVAL;
364
365 /* pptable will handle the features to enable */
366 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
367
368 return 0;
369 }
370
371 static int
arcturus_set_single_dpm_table(struct smu_context * smu,struct arcturus_single_dpm_table * single_dpm_table,PPCLK_e clk_id)372 arcturus_set_single_dpm_table(struct smu_context *smu,
373 struct arcturus_single_dpm_table *single_dpm_table,
374 PPCLK_e clk_id)
375 {
376 int ret = 0;
377 uint32_t i, num_of_levels = 0, clk;
378
379 ret = smu_send_smc_msg_with_param(smu,
380 SMU_MSG_GetDpmFreqByIndex,
381 (clk_id << 16 | 0xFF));
382 if (ret) {
383 pr_err("[%s] failed to get dpm levels!\n", __func__);
384 return ret;
385 }
386
387 smu_read_smc_arg(smu, &num_of_levels);
388 if (!num_of_levels) {
389 pr_err("[%s] number of clk levels is invalid!\n", __func__);
390 return -EINVAL;
391 }
392
393 single_dpm_table->count = num_of_levels;
394 for (i = 0; i < num_of_levels; i++) {
395 ret = smu_send_smc_msg_with_param(smu,
396 SMU_MSG_GetDpmFreqByIndex,
397 (clk_id << 16 | i));
398 if (ret) {
399 pr_err("[%s] failed to get dpm freq by index!\n", __func__);
400 return ret;
401 }
402 smu_read_smc_arg(smu, &clk);
403 if (!clk) {
404 pr_err("[%s] clk value is invalid!\n", __func__);
405 return -EINVAL;
406 }
407 single_dpm_table->dpm_levels[i].value = clk;
408 single_dpm_table->dpm_levels[i].enabled = true;
409 }
410 return 0;
411 }
412
arcturus_init_single_dpm_state(struct arcturus_dpm_state * dpm_state)413 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
414 {
415 dpm_state->soft_min_level = 0x0;
416 dpm_state->soft_max_level = 0xffff;
417 dpm_state->hard_min_level = 0x0;
418 dpm_state->hard_max_level = 0xffff;
419 }
420
arcturus_set_default_dpm_table(struct smu_context * smu)421 static int arcturus_set_default_dpm_table(struct smu_context *smu)
422 {
423 int ret;
424
425 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
426 struct arcturus_dpm_table *dpm_table = NULL;
427 struct arcturus_single_dpm_table *single_dpm_table;
428
429 dpm_table = smu_dpm->dpm_context;
430
431 /* socclk */
432 single_dpm_table = &(dpm_table->soc_table);
433 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
434 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
435 PPCLK_SOCCLK);
436 if (ret) {
437 pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
438 return ret;
439 }
440 } else {
441 single_dpm_table->count = 1;
442 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
443 }
444 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
445
446 /* gfxclk */
447 single_dpm_table = &(dpm_table->gfx_table);
448 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
449 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
450 PPCLK_GFXCLK);
451 if (ret) {
452 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
453 return ret;
454 }
455 } else {
456 single_dpm_table->count = 1;
457 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
458 }
459 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
460
461 /* memclk */
462 single_dpm_table = &(dpm_table->mem_table);
463 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
464 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
465 PPCLK_UCLK);
466 if (ret) {
467 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
468 return ret;
469 }
470 } else {
471 single_dpm_table->count = 1;
472 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
473 }
474 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
475
476 /* fclk */
477 single_dpm_table = &(dpm_table->fclk_table);
478 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
479 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
480 PPCLK_FCLK);
481 if (ret) {
482 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
483 return ret;
484 }
485 } else {
486 single_dpm_table->count = 1;
487 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
488 }
489 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
490
491 memcpy(smu_dpm->golden_dpm_context, dpm_table,
492 sizeof(struct arcturus_dpm_table));
493
494 return 0;
495 }
496
arcturus_check_powerplay_table(struct smu_context * smu)497 static int arcturus_check_powerplay_table(struct smu_context *smu)
498 {
499 return 0;
500 }
501
arcturus_store_powerplay_table(struct smu_context * smu)502 static int arcturus_store_powerplay_table(struct smu_context *smu)
503 {
504 const struct smu_11_0_powerplay_table *powerplay_table = NULL;
505 struct smu_table_context *table_context = &smu->smu_table;
506 struct smu_baco_context *smu_baco = &smu->smu_baco;
507 int ret = 0;
508
509 if (!table_context->power_play_table)
510 return -EINVAL;
511
512 powerplay_table = table_context->power_play_table;
513
514 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
515 sizeof(PPTable_t));
516
517 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
518
519 mutex_lock(&smu_baco->mutex);
520 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
521 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
522 smu_baco->platform_support = true;
523 mutex_unlock(&smu_baco->mutex);
524
525 return ret;
526 }
527
arcturus_append_powerplay_table(struct smu_context * smu)528 static int arcturus_append_powerplay_table(struct smu_context *smu)
529 {
530 struct smu_table_context *table_context = &smu->smu_table;
531 PPTable_t *smc_pptable = table_context->driver_pptable;
532 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
533 int index, ret;
534
535 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
536 smc_dpm_info);
537
538 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
539 (uint8_t **)&smc_dpm_table);
540 if (ret)
541 return ret;
542
543 pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
544 smc_dpm_table->table_header.format_revision,
545 smc_dpm_table->table_header.content_revision);
546
547 if ((smc_dpm_table->table_header.format_revision == 4) &&
548 (smc_dpm_table->table_header.content_revision == 6))
549 memcpy(&smc_pptable->MaxVoltageStepGfx,
550 &smc_dpm_table->maxvoltagestepgfx,
551 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
552
553 return 0;
554 }
555
arcturus_run_btc(struct smu_context * smu)556 static int arcturus_run_btc(struct smu_context *smu)
557 {
558 int ret = 0;
559
560 ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
561 if (ret) {
562 pr_err("RunAfllBtc failed!\n");
563 return ret;
564 }
565
566 return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc);
567 }
568
arcturus_populate_umd_state_clk(struct smu_context * smu)569 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
570 {
571 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
572 struct arcturus_dpm_table *dpm_table = NULL;
573 struct arcturus_single_dpm_table *gfx_table = NULL;
574 struct arcturus_single_dpm_table *mem_table = NULL;
575
576 dpm_table = smu_dpm->dpm_context;
577 gfx_table = &(dpm_table->gfx_table);
578 mem_table = &(dpm_table->mem_table);
579
580 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
581 smu->pstate_mclk = mem_table->dpm_levels[0].value;
582
583 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
584 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
585 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
586 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
587 }
588
589 smu->pstate_sclk = smu->pstate_sclk * 100;
590 smu->pstate_mclk = smu->pstate_mclk * 100;
591
592 return 0;
593 }
594
595 #ifdef CONFIG_SYSFS
arcturus_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct arcturus_single_dpm_table * dpm_table)596 static int arcturus_get_clk_table(struct smu_context *smu,
597 struct pp_clock_levels_with_latency *clocks,
598 struct arcturus_single_dpm_table *dpm_table)
599 {
600 int i, count;
601
602 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
603 clocks->num_levels = count;
604
605 for (i = 0; i < count; i++) {
606 clocks->data[i].clocks_in_khz =
607 dpm_table->dpm_levels[i].value * 1000;
608 clocks->data[i].latency_in_us = 0;
609 }
610
611 return 0;
612 }
613
arcturus_freqs_in_same_level(int32_t frequency1,int32_t frequency2)614 static int arcturus_freqs_in_same_level(int32_t frequency1,
615 int32_t frequency2)
616 {
617 return (abs(frequency1 - frequency2) <= EPSILON);
618 }
619 #endif
620
arcturus_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)621 static int arcturus_print_clk_levels(struct smu_context *smu,
622 enum smu_clk_type type, char *buf)
623 {
624 #ifndef CONFIG_SYSFS
625 return 0;
626 #else
627 int i, now, size = 0;
628 int ret = 0;
629 struct pp_clock_levels_with_latency clocks;
630 struct arcturus_single_dpm_table *single_dpm_table;
631 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
632 struct arcturus_dpm_table *dpm_table = NULL;
633
634 dpm_table = smu_dpm->dpm_context;
635
636 switch (type) {
637 case SMU_SCLK:
638 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
639 if (ret) {
640 pr_err("Attempt to get current gfx clk Failed!");
641 return ret;
642 }
643
644 single_dpm_table = &(dpm_table->gfx_table);
645 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
646 if (ret) {
647 pr_err("Attempt to get gfx clk levels Failed!");
648 return ret;
649 }
650
651 /*
652 * For DPM disabled case, there will be only one clock level.
653 * And it's safe to assume that is always the current clock.
654 */
655 for (i = 0; i < clocks.num_levels; i++)
656 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
657 clocks.data[i].clocks_in_khz / 1000,
658 (clocks.num_levels == 1) ? "*" :
659 (arcturus_freqs_in_same_level(
660 clocks.data[i].clocks_in_khz / 1000,
661 now / 100) ? "*" : ""));
662 break;
663
664 case SMU_MCLK:
665 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
666 if (ret) {
667 pr_err("Attempt to get current mclk Failed!");
668 return ret;
669 }
670
671 single_dpm_table = &(dpm_table->mem_table);
672 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
673 if (ret) {
674 pr_err("Attempt to get memory clk levels Failed!");
675 return ret;
676 }
677
678 for (i = 0; i < clocks.num_levels; i++)
679 size += sprintf(buf + size, "%d: %uMhz %s\n",
680 i, clocks.data[i].clocks_in_khz / 1000,
681 (clocks.num_levels == 1) ? "*" :
682 (arcturus_freqs_in_same_level(
683 clocks.data[i].clocks_in_khz / 1000,
684 now / 100) ? "*" : ""));
685 break;
686
687 case SMU_SOCCLK:
688 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
689 if (ret) {
690 pr_err("Attempt to get current socclk Failed!");
691 return ret;
692 }
693
694 single_dpm_table = &(dpm_table->soc_table);
695 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
696 if (ret) {
697 pr_err("Attempt to get socclk levels Failed!");
698 return ret;
699 }
700
701 for (i = 0; i < clocks.num_levels; i++)
702 size += sprintf(buf + size, "%d: %uMhz %s\n",
703 i, clocks.data[i].clocks_in_khz / 1000,
704 (clocks.num_levels == 1) ? "*" :
705 (arcturus_freqs_in_same_level(
706 clocks.data[i].clocks_in_khz / 1000,
707 now / 100) ? "*" : ""));
708 break;
709
710 case SMU_FCLK:
711 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
712 if (ret) {
713 pr_err("Attempt to get current fclk Failed!");
714 return ret;
715 }
716
717 single_dpm_table = &(dpm_table->fclk_table);
718 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
719 if (ret) {
720 pr_err("Attempt to get fclk levels Failed!");
721 return ret;
722 }
723
724 for (i = 0; i < single_dpm_table->count; i++)
725 size += sprintf(buf + size, "%d: %uMhz %s\n",
726 i, single_dpm_table->dpm_levels[i].value,
727 (clocks.num_levels == 1) ? "*" :
728 (arcturus_freqs_in_same_level(
729 clocks.data[i].clocks_in_khz / 1000,
730 now / 100) ? "*" : ""));
731 break;
732
733 default:
734 break;
735 }
736
737 return size;
738 #endif
739 }
740
arcturus_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask)741 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
742 uint32_t feature_mask)
743 {
744 struct arcturus_single_dpm_table *single_dpm_table;
745 struct arcturus_dpm_table *dpm_table =
746 smu->smu_dpm.dpm_context;
747 uint32_t freq;
748 int ret = 0;
749
750 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
751 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
752 single_dpm_table = &(dpm_table->gfx_table);
753 freq = max ? single_dpm_table->dpm_state.soft_max_level :
754 single_dpm_table->dpm_state.soft_min_level;
755 ret = smu_send_smc_msg_with_param(smu,
756 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
757 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
758 if (ret) {
759 pr_err("Failed to set soft %s gfxclk !\n",
760 max ? "max" : "min");
761 return ret;
762 }
763 }
764
765 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
766 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
767 single_dpm_table = &(dpm_table->mem_table);
768 freq = max ? single_dpm_table->dpm_state.soft_max_level :
769 single_dpm_table->dpm_state.soft_min_level;
770 ret = smu_send_smc_msg_with_param(smu,
771 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
772 (PPCLK_UCLK << 16) | (freq & 0xffff));
773 if (ret) {
774 pr_err("Failed to set soft %s memclk !\n",
775 max ? "max" : "min");
776 return ret;
777 }
778 }
779
780 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
781 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
782 single_dpm_table = &(dpm_table->soc_table);
783 freq = max ? single_dpm_table->dpm_state.soft_max_level :
784 single_dpm_table->dpm_state.soft_min_level;
785 ret = smu_send_smc_msg_with_param(smu,
786 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
787 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
788 if (ret) {
789 pr_err("Failed to set soft %s socclk !\n",
790 max ? "max" : "min");
791 return ret;
792 }
793 }
794
795 return ret;
796 }
797
arcturus_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)798 static int arcturus_force_clk_levels(struct smu_context *smu,
799 enum smu_clk_type type, uint32_t mask)
800 {
801 struct arcturus_dpm_table *dpm_table;
802 struct arcturus_single_dpm_table *single_dpm_table;
803 uint32_t soft_min_level, soft_max_level;
804 int ret = 0;
805
806 soft_min_level = mask ? (ffs(mask) - 1) : 0;
807 soft_max_level = mask ? (fls(mask) - 1) : 0;
808
809 dpm_table = smu->smu_dpm.dpm_context;
810
811 switch (type) {
812 case SMU_SCLK:
813 single_dpm_table = &(dpm_table->gfx_table);
814
815 if (soft_max_level >= single_dpm_table->count) {
816 pr_err("Clock level specified %d is over max allowed %d\n",
817 soft_max_level, single_dpm_table->count - 1);
818 ret = -EINVAL;
819 break;
820 }
821
822 single_dpm_table->dpm_state.soft_min_level =
823 single_dpm_table->dpm_levels[soft_min_level].value;
824 single_dpm_table->dpm_state.soft_max_level =
825 single_dpm_table->dpm_levels[soft_max_level].value;
826
827 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
828 if (ret) {
829 pr_err("Failed to upload boot level to lowest!\n");
830 break;
831 }
832
833 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
834 if (ret)
835 pr_err("Failed to upload dpm max level to highest!\n");
836
837 break;
838
839 case SMU_MCLK:
840 case SMU_SOCCLK:
841 case SMU_FCLK:
842 /*
843 * Should not arrive here since Arcturus does not
844 * support mclk/socclk/fclk softmin/softmax settings
845 */
846 ret = -EINVAL;
847 break;
848
849 default:
850 break;
851 }
852
853 return ret;
854 }
855
arcturus_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)856 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
857 struct smu_temperature_range *range)
858 {
859 PPTable_t *pptable = smu->smu_table.driver_pptable;
860
861 if (!range)
862 return -EINVAL;
863
864 range->max = pptable->TedgeLimit *
865 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
866 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
867 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
868 range->hotspot_crit_max = pptable->ThotspotLimit *
869 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
870 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
871 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
872 range->mem_crit_max = pptable->TmemLimit *
873 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
874 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
875 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
876
877 return 0;
878 }
879
arcturus_get_metrics_table(struct smu_context * smu,SmuMetrics_t * metrics_table)880 static int arcturus_get_metrics_table(struct smu_context *smu,
881 SmuMetrics_t *metrics_table)
882 {
883 struct smu_table_context *smu_table= &smu->smu_table;
884 int ret = 0;
885
886 mutex_lock(&smu->metrics_lock);
887 if (!smu_table->metrics_time ||
888 time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
889 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
890 (void *)smu_table->metrics_table, false);
891 if (ret) {
892 pr_info("Failed to export SMU metrics table!\n");
893 mutex_unlock(&smu->metrics_lock);
894 return ret;
895 }
896 smu_table->metrics_time = jiffies;
897 }
898
899 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
900 mutex_unlock(&smu->metrics_lock);
901
902 return ret;
903 }
904
arcturus_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)905 static int arcturus_get_current_activity_percent(struct smu_context *smu,
906 enum amd_pp_sensors sensor,
907 uint32_t *value)
908 {
909 SmuMetrics_t metrics;
910 int ret = 0;
911
912 if (!value)
913 return -EINVAL;
914
915 ret = arcturus_get_metrics_table(smu, &metrics);
916 if (ret)
917 return ret;
918
919 switch (sensor) {
920 case AMDGPU_PP_SENSOR_GPU_LOAD:
921 *value = metrics.AverageGfxActivity;
922 break;
923 case AMDGPU_PP_SENSOR_MEM_LOAD:
924 *value = metrics.AverageUclkActivity;
925 break;
926 default:
927 pr_err("Invalid sensor for retrieving clock activity\n");
928 return -EINVAL;
929 }
930
931 return 0;
932 }
933
arcturus_get_gpu_power(struct smu_context * smu,uint32_t * value)934 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
935 {
936 SmuMetrics_t metrics;
937 int ret = 0;
938
939 if (!value)
940 return -EINVAL;
941
942 ret = arcturus_get_metrics_table(smu, &metrics);
943 if (ret)
944 return ret;
945
946 *value = metrics.AverageSocketPower << 8;
947
948 return 0;
949 }
950
arcturus_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)951 static int arcturus_thermal_get_temperature(struct smu_context *smu,
952 enum amd_pp_sensors sensor,
953 uint32_t *value)
954 {
955 SmuMetrics_t metrics;
956 int ret = 0;
957
958 if (!value)
959 return -EINVAL;
960
961 ret = arcturus_get_metrics_table(smu, &metrics);
962 if (ret)
963 return ret;
964
965 switch (sensor) {
966 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
967 *value = metrics.TemperatureHotspot *
968 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
969 break;
970 case AMDGPU_PP_SENSOR_EDGE_TEMP:
971 *value = metrics.TemperatureEdge *
972 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
973 break;
974 case AMDGPU_PP_SENSOR_MEM_TEMP:
975 *value = metrics.TemperatureHBM *
976 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
977 break;
978 default:
979 pr_err("Invalid sensor for retrieving temp\n");
980 return -EINVAL;
981 }
982
983 return 0;
984 }
985
arcturus_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)986 static int arcturus_read_sensor(struct smu_context *smu,
987 enum amd_pp_sensors sensor,
988 void *data, uint32_t *size)
989 {
990 struct smu_table_context *table_context = &smu->smu_table;
991 PPTable_t *pptable = table_context->driver_pptable;
992 int ret = 0;
993
994 if (!data || !size)
995 return -EINVAL;
996
997 mutex_lock(&smu->sensor_lock);
998 switch (sensor) {
999 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1000 *(uint32_t *)data = pptable->FanMaximumRpm;
1001 *size = 4;
1002 break;
1003 case AMDGPU_PP_SENSOR_MEM_LOAD:
1004 case AMDGPU_PP_SENSOR_GPU_LOAD:
1005 ret = arcturus_get_current_activity_percent(smu,
1006 sensor,
1007 (uint32_t *)data);
1008 *size = 4;
1009 break;
1010 case AMDGPU_PP_SENSOR_GPU_POWER:
1011 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1012 *size = 4;
1013 break;
1014 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1015 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1016 case AMDGPU_PP_SENSOR_MEM_TEMP:
1017 ret = arcturus_thermal_get_temperature(smu, sensor,
1018 (uint32_t *)data);
1019 *size = 4;
1020 break;
1021 default:
1022 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1023 }
1024 mutex_unlock(&smu->sensor_lock);
1025
1026 return ret;
1027 }
1028
arcturus_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1029 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1030 uint32_t *speed)
1031 {
1032 SmuMetrics_t metrics;
1033 int ret = 0;
1034
1035 if (!speed)
1036 return -EINVAL;
1037
1038 ret = arcturus_get_metrics_table(smu, &metrics);
1039 if (ret)
1040 return ret;
1041
1042 *speed = metrics.CurrFanSpeed;
1043
1044 return ret;
1045 }
1046
arcturus_get_fan_speed_percent(struct smu_context * smu,uint32_t * speed)1047 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1048 uint32_t *speed)
1049 {
1050 PPTable_t *pptable = smu->smu_table.driver_pptable;
1051 uint32_t percent, current_rpm;
1052 int ret = 0;
1053
1054 if (!speed)
1055 return -EINVAL;
1056
1057 ret = arcturus_get_fan_speed_rpm(smu, ¤t_rpm);
1058 if (ret)
1059 return ret;
1060
1061 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1062 *speed = percent > 100 ? 100 : percent;
1063
1064 return ret;
1065 }
1066
arcturus_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1067 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1068 enum smu_clk_type clk_type,
1069 uint32_t *value)
1070 {
1071 static SmuMetrics_t metrics;
1072 int ret = 0, clk_id = 0;
1073
1074 if (!value)
1075 return -EINVAL;
1076
1077 clk_id = smu_clk_get_index(smu, clk_type);
1078 if (clk_id < 0)
1079 return -EINVAL;
1080
1081 ret = arcturus_get_metrics_table(smu, &metrics);
1082 if (ret)
1083 return ret;
1084
1085 switch (clk_id) {
1086 case PPCLK_GFXCLK:
1087 /*
1088 * CurrClock[clk_id] can provide accurate
1089 * output only when the dpm feature is enabled.
1090 * We can use Average_* for dpm disabled case.
1091 * But this is available for gfxclk/uclk/socclk.
1092 */
1093 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1094 *value = metrics.CurrClock[PPCLK_GFXCLK];
1095 else
1096 *value = metrics.AverageGfxclkFrequency;
1097 break;
1098 case PPCLK_UCLK:
1099 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1100 *value = metrics.CurrClock[PPCLK_UCLK];
1101 else
1102 *value = metrics.AverageUclkFrequency;
1103 break;
1104 case PPCLK_SOCCLK:
1105 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1106 *value = metrics.CurrClock[PPCLK_SOCCLK];
1107 else
1108 *value = metrics.AverageSocclkFrequency;
1109 break;
1110 default:
1111 *value = metrics.CurrClock[clk_id];
1112 break;
1113 }
1114
1115 return ret;
1116 }
1117
arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table * table)1118 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1119 {
1120 uint32_t i;
1121
1122 for (i = 0; i < table->count; i++) {
1123 if (table->dpm_levels[i].enabled)
1124 break;
1125 }
1126 if (i >= table->count) {
1127 i = 0;
1128 table->dpm_levels[i].enabled = true;
1129 }
1130
1131 return i;
1132 }
1133
arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table * table)1134 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1135 {
1136 int i = 0;
1137
1138 if (table->count <= 0) {
1139 pr_err("[%s] DPM Table has no entry!", __func__);
1140 return 0;
1141 }
1142 if (table->count > MAX_DPM_NUMBER) {
1143 pr_err("[%s] DPM Table has too many entries!", __func__);
1144 return MAX_DPM_NUMBER - 1;
1145 }
1146
1147 for (i = table->count - 1; i >= 0; i--) {
1148 if (table->dpm_levels[i].enabled)
1149 break;
1150 }
1151 if (i < 0) {
1152 i = 0;
1153 table->dpm_levels[i].enabled = true;
1154 }
1155
1156 return i;
1157 }
1158
1159
1160
arcturus_force_dpm_limit_value(struct smu_context * smu,bool highest)1161 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1162 {
1163 struct arcturus_dpm_table *dpm_table =
1164 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1165 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1166 uint32_t soft_level;
1167 int ret = 0;
1168
1169 /* gfxclk */
1170 if (highest)
1171 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1172 else
1173 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1174
1175 dpm_table->gfx_table.dpm_state.soft_min_level =
1176 dpm_table->gfx_table.dpm_state.soft_max_level =
1177 dpm_table->gfx_table.dpm_levels[soft_level].value;
1178
1179 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1180 if (ret) {
1181 pr_err("Failed to upload boot level to %s!\n",
1182 highest ? "highest" : "lowest");
1183 return ret;
1184 }
1185
1186 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1187 if (ret) {
1188 pr_err("Failed to upload dpm max level to %s!\n!",
1189 highest ? "highest" : "lowest");
1190 return ret;
1191 }
1192
1193 if (hive)
1194 /*
1195 * Force XGMI Pstate to highest or lowest
1196 * TODO: revise this when xgmi dpm is functional
1197 */
1198 ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
1199
1200 return ret;
1201 }
1202
arcturus_unforce_dpm_levels(struct smu_context * smu)1203 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1204 {
1205 struct arcturus_dpm_table *dpm_table =
1206 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1207 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1208 uint32_t soft_min_level, soft_max_level;
1209 int ret = 0;
1210
1211 /* gfxclk */
1212 soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1213 soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1214 dpm_table->gfx_table.dpm_state.soft_min_level =
1215 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1216 dpm_table->gfx_table.dpm_state.soft_max_level =
1217 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1218
1219 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1220 if (ret) {
1221 pr_err("Failed to upload DPM Bootup Levels!");
1222 return ret;
1223 }
1224
1225 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1226 if (ret) {
1227 pr_err("Failed to upload DPM Max Levels!");
1228 return ret;
1229 }
1230
1231 if (hive)
1232 /*
1233 * Reset XGMI Pstate back to default
1234 * TODO: revise this when xgmi dpm is functional
1235 */
1236 ret = smu_v11_0_set_xgmi_pstate(smu, 0);
1237
1238 return ret;
1239 }
1240
1241 static int
arcturus_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)1242 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1243 enum amd_dpm_forced_level level,
1244 uint32_t *sclk_mask,
1245 uint32_t *mclk_mask,
1246 uint32_t *soc_mask)
1247 {
1248 struct arcturus_dpm_table *dpm_table =
1249 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1250 struct arcturus_single_dpm_table *gfx_dpm_table;
1251 struct arcturus_single_dpm_table *mem_dpm_table;
1252 struct arcturus_single_dpm_table *soc_dpm_table;
1253
1254 if (!smu->smu_dpm.dpm_context)
1255 return -EINVAL;
1256
1257 gfx_dpm_table = &dpm_table->gfx_table;
1258 mem_dpm_table = &dpm_table->mem_table;
1259 soc_dpm_table = &dpm_table->soc_table;
1260
1261 *sclk_mask = 0;
1262 *mclk_mask = 0;
1263 *soc_mask = 0;
1264
1265 if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1266 mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1267 soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1268 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1269 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1270 *soc_mask = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1271 }
1272
1273 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1274 *sclk_mask = 0;
1275 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1276 *mclk_mask = 0;
1277 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1278 *sclk_mask = gfx_dpm_table->count - 1;
1279 *mclk_mask = mem_dpm_table->count - 1;
1280 *soc_mask = soc_dpm_table->count - 1;
1281 }
1282
1283 return 0;
1284 }
1285
arcturus_get_power_limit(struct smu_context * smu,uint32_t * limit,bool cap)1286 static int arcturus_get_power_limit(struct smu_context *smu,
1287 uint32_t *limit,
1288 bool cap)
1289 {
1290 PPTable_t *pptable = smu->smu_table.driver_pptable;
1291 uint32_t asic_default_power_limit = 0;
1292 int ret = 0;
1293 int power_src;
1294
1295 if (!smu->power_limit) {
1296 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1297 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1298 if (power_src < 0)
1299 return -EINVAL;
1300
1301 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1302 power_src << 16);
1303 if (ret) {
1304 pr_err("[%s] get PPT limit failed!", __func__);
1305 return ret;
1306 }
1307 smu_read_smc_arg(smu, &asic_default_power_limit);
1308 } else {
1309 /* the last hope to figure out the ppt limit */
1310 if (!pptable) {
1311 pr_err("Cannot get PPT limit due to pptable missing!");
1312 return -EINVAL;
1313 }
1314 asic_default_power_limit =
1315 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1316 }
1317
1318 smu->power_limit = asic_default_power_limit;
1319 }
1320
1321 if (cap)
1322 *limit = smu_v11_0_get_max_power_limit(smu);
1323 else
1324 *limit = smu->power_limit;
1325
1326 return 0;
1327 }
1328
arcturus_get_power_profile_mode(struct smu_context * smu,char * buf)1329 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1330 char *buf)
1331 {
1332 #ifndef CONFIG_SYSFS
1333 return 0;
1334 #else
1335 struct amdgpu_device *adev = smu->adev;
1336 DpmActivityMonitorCoeffInt_t activity_monitor;
1337 static const char *profile_name[] = {
1338 "BOOTUP_DEFAULT",
1339 "3D_FULL_SCREEN",
1340 "POWER_SAVING",
1341 "VIDEO",
1342 "VR",
1343 "COMPUTE",
1344 "CUSTOM"};
1345 static const char *title[] = {
1346 "PROFILE_INDEX(NAME)",
1347 "CLOCK_TYPE(NAME)",
1348 "FPS",
1349 "UseRlcBusy",
1350 "MinActiveFreqType",
1351 "MinActiveFreq",
1352 "BoosterFreqType",
1353 "BoosterFreq",
1354 "PD_Data_limit_c",
1355 "PD_Data_error_coeff",
1356 "PD_Data_error_rate_coeff"};
1357 uint32_t i, size = 0;
1358 int16_t workload_type = 0;
1359 int result = 0;
1360 uint32_t smu_version;
1361
1362 if (!buf)
1363 return -EINVAL;
1364
1365 result = smu_get_smc_version(smu, NULL, &smu_version);
1366 if (result)
1367 return result;
1368
1369 if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev))
1370 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1371 title[0], title[1], title[2], title[3], title[4], title[5],
1372 title[6], title[7], title[8], title[9], title[10]);
1373 else
1374 size += sprintf(buf + size, "%16s\n",
1375 title[0]);
1376
1377 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1378 /*
1379 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1380 * Not all profile modes are supported on arcturus.
1381 */
1382 workload_type = smu_workload_get_type(smu, i);
1383 if (workload_type < 0)
1384 continue;
1385
1386 if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
1387 result = smu_update_table(smu,
1388 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1389 workload_type,
1390 (void *)(&activity_monitor),
1391 false);
1392 if (result) {
1393 pr_err("[%s] Failed to get activity monitor!", __func__);
1394 return result;
1395 }
1396 }
1397
1398 size += sprintf(buf + size, "%2d %14s%s\n",
1399 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1400
1401 if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
1402 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1403 " ",
1404 0,
1405 "GFXCLK",
1406 activity_monitor.Gfx_FPS,
1407 activity_monitor.Gfx_UseRlcBusy,
1408 activity_monitor.Gfx_MinActiveFreqType,
1409 activity_monitor.Gfx_MinActiveFreq,
1410 activity_monitor.Gfx_BoosterFreqType,
1411 activity_monitor.Gfx_BoosterFreq,
1412 activity_monitor.Gfx_PD_Data_limit_c,
1413 activity_monitor.Gfx_PD_Data_error_coeff,
1414 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1415
1416 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1417 " ",
1418 1,
1419 "UCLK",
1420 activity_monitor.Mem_FPS,
1421 activity_monitor.Mem_UseRlcBusy,
1422 activity_monitor.Mem_MinActiveFreqType,
1423 activity_monitor.Mem_MinActiveFreq,
1424 activity_monitor.Mem_BoosterFreqType,
1425 activity_monitor.Mem_BoosterFreq,
1426 activity_monitor.Mem_PD_Data_limit_c,
1427 activity_monitor.Mem_PD_Data_error_coeff,
1428 activity_monitor.Mem_PD_Data_error_rate_coeff);
1429 }
1430 }
1431
1432 return size;
1433 #endif
1434 }
1435
arcturus_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1436 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1437 long *input,
1438 uint32_t size)
1439 {
1440 DpmActivityMonitorCoeffInt_t activity_monitor;
1441 int workload_type = 0;
1442 uint32_t profile_mode = input[size];
1443 int ret = 0;
1444 uint32_t smu_version;
1445
1446 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1447 pr_err("Invalid power profile mode %d\n", profile_mode);
1448 return -EINVAL;
1449 }
1450
1451 ret = smu_get_smc_version(smu, NULL, &smu_version);
1452 if (ret)
1453 return ret;
1454
1455 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1456 (smu_version >=0x360d00)) {
1457 ret = smu_update_table(smu,
1458 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1459 WORKLOAD_PPLIB_CUSTOM_BIT,
1460 (void *)(&activity_monitor),
1461 false);
1462 if (ret) {
1463 pr_err("[%s] Failed to get activity monitor!", __func__);
1464 return ret;
1465 }
1466
1467 switch (input[0]) {
1468 case 0: /* Gfxclk */
1469 activity_monitor.Gfx_FPS = input[1];
1470 activity_monitor.Gfx_UseRlcBusy = input[2];
1471 activity_monitor.Gfx_MinActiveFreqType = input[3];
1472 activity_monitor.Gfx_MinActiveFreq = input[4];
1473 activity_monitor.Gfx_BoosterFreqType = input[5];
1474 activity_monitor.Gfx_BoosterFreq = input[6];
1475 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1476 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1477 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1478 break;
1479 case 1: /* Uclk */
1480 activity_monitor.Mem_FPS = input[1];
1481 activity_monitor.Mem_UseRlcBusy = input[2];
1482 activity_monitor.Mem_MinActiveFreqType = input[3];
1483 activity_monitor.Mem_MinActiveFreq = input[4];
1484 activity_monitor.Mem_BoosterFreqType = input[5];
1485 activity_monitor.Mem_BoosterFreq = input[6];
1486 activity_monitor.Mem_PD_Data_limit_c = input[7];
1487 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1488 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1489 break;
1490 }
1491
1492 ret = smu_update_table(smu,
1493 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1494 WORKLOAD_PPLIB_CUSTOM_BIT,
1495 (void *)(&activity_monitor),
1496 true);
1497 if (ret) {
1498 pr_err("[%s] Failed to set activity monitor!", __func__);
1499 return ret;
1500 }
1501 }
1502
1503 /*
1504 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1505 * Not all profile modes are supported on arcturus.
1506 */
1507 workload_type = smu_workload_get_type(smu, profile_mode);
1508 if (workload_type < 0) {
1509 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1510 return -EINVAL;
1511 }
1512
1513 ret = smu_send_smc_msg_with_param(smu,
1514 SMU_MSG_SetWorkloadMask,
1515 1 << workload_type);
1516 if (ret) {
1517 pr_err("Fail to set workload type %d\n", workload_type);
1518 return ret;
1519 }
1520
1521 smu->power_profile_mode = profile_mode;
1522
1523 return 0;
1524 }
1525
arcturus_dump_pptable(struct smu_context * smu)1526 static void arcturus_dump_pptable(struct smu_context *smu)
1527 {
1528 struct smu_table_context *table_context = &smu->smu_table;
1529 PPTable_t *pptable = table_context->driver_pptable;
1530 int i;
1531
1532 pr_info("Dumped PPTable:\n");
1533
1534 pr_info("Version = 0x%08x\n", pptable->Version);
1535
1536 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1537 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1538
1539 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1540 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1541 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1542 }
1543
1544 pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1545 pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1546 pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1547 pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1548
1549 pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1550 pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1551 pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1552 pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1553 pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1554 pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1555 pr_info("FitLimit = %d\n", pptable->FitLimit);
1556
1557 pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1558 pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1559
1560 pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1561
1562 pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1563 pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1564
1565 pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1566 pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1567 pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1568 pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1569
1570 pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1571 pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1572 pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1573 pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1574
1575 pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1576 pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1577
1578 pr_info("[PPCLK_GFXCLK]\n"
1579 " .VoltageMode = 0x%02x\n"
1580 " .SnapToDiscrete = 0x%02x\n"
1581 " .NumDiscreteLevels = 0x%02x\n"
1582 " .padding = 0x%02x\n"
1583 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1584 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1585 " .SsFmin = 0x%04x\n"
1586 " .Padding_16 = 0x%04x\n",
1587 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1588 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1589 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1590 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1591 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1592 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1593 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1594 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1595 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1596 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1597 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1598
1599 pr_info("[PPCLK_VCLK]\n"
1600 " .VoltageMode = 0x%02x\n"
1601 " .SnapToDiscrete = 0x%02x\n"
1602 " .NumDiscreteLevels = 0x%02x\n"
1603 " .padding = 0x%02x\n"
1604 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1605 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1606 " .SsFmin = 0x%04x\n"
1607 " .Padding_16 = 0x%04x\n",
1608 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1609 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1610 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1611 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1612 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1613 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1614 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1615 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1616 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1617 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1618 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1619
1620 pr_info("[PPCLK_DCLK]\n"
1621 " .VoltageMode = 0x%02x\n"
1622 " .SnapToDiscrete = 0x%02x\n"
1623 " .NumDiscreteLevels = 0x%02x\n"
1624 " .padding = 0x%02x\n"
1625 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1626 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1627 " .SsFmin = 0x%04x\n"
1628 " .Padding_16 = 0x%04x\n",
1629 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1630 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1631 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1632 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1633 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1634 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1635 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1636 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1637 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1638 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1639 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1640
1641 pr_info("[PPCLK_SOCCLK]\n"
1642 " .VoltageMode = 0x%02x\n"
1643 " .SnapToDiscrete = 0x%02x\n"
1644 " .NumDiscreteLevels = 0x%02x\n"
1645 " .padding = 0x%02x\n"
1646 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1647 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1648 " .SsFmin = 0x%04x\n"
1649 " .Padding_16 = 0x%04x\n",
1650 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1651 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1652 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1653 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1654 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1655 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1656 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1657 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1658 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1659 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1660 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1661
1662 pr_info("[PPCLK_UCLK]\n"
1663 " .VoltageMode = 0x%02x\n"
1664 " .SnapToDiscrete = 0x%02x\n"
1665 " .NumDiscreteLevels = 0x%02x\n"
1666 " .padding = 0x%02x\n"
1667 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1668 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1669 " .SsFmin = 0x%04x\n"
1670 " .Padding_16 = 0x%04x\n",
1671 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1672 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1673 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1674 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1675 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1676 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1677 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1678 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1679 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1680 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1681 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1682
1683 pr_info("[PPCLK_FCLK]\n"
1684 " .VoltageMode = 0x%02x\n"
1685 " .SnapToDiscrete = 0x%02x\n"
1686 " .NumDiscreteLevels = 0x%02x\n"
1687 " .padding = 0x%02x\n"
1688 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1689 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1690 " .SsFmin = 0x%04x\n"
1691 " .Padding_16 = 0x%04x\n",
1692 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1693 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1694 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1695 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1696 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1697 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1698 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1699 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1700 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1701 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1702 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1703
1704
1705 pr_info("FreqTableGfx\n");
1706 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1707 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1708
1709 pr_info("FreqTableVclk\n");
1710 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1711 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1712
1713 pr_info("FreqTableDclk\n");
1714 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1715 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1716
1717 pr_info("FreqTableSocclk\n");
1718 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1719 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1720
1721 pr_info("FreqTableUclk\n");
1722 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1723 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1724
1725 pr_info("FreqTableFclk\n");
1726 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1727 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1728
1729 pr_info("Mp0clkFreq\n");
1730 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1731 pr_info(" .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1732
1733 pr_info("Mp0DpmVoltage\n");
1734 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1735 pr_info(" .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1736
1737 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1738 pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1739 pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1740 pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1741 pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1742 pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1743 pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1744 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1745 pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1746
1747 pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1748 pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1749 pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1750 pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1751
1752 pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1753 pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1754
1755 pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1756 pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1757 pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1758 pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1759 pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1760 pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1761
1762 pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1763 pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1764 pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1765 pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1766 pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1767 pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1768 pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1769 pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1770 pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1771
1772 pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1773 pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1774 pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1775 pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1776
1777 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1778 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1779 pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1780 pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1781
1782 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1783 pptable->dBtcGbGfxPll.a,
1784 pptable->dBtcGbGfxPll.b,
1785 pptable->dBtcGbGfxPll.c);
1786 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1787 pptable->dBtcGbGfxAfll.a,
1788 pptable->dBtcGbGfxAfll.b,
1789 pptable->dBtcGbGfxAfll.c);
1790 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1791 pptable->dBtcGbSoc.a,
1792 pptable->dBtcGbSoc.b,
1793 pptable->dBtcGbSoc.c);
1794
1795 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1796 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1797 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1798 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1799 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1800 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1801
1802 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1803 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1804 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1805 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1806 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1807 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1808 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1809 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1810
1811 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1812 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1813
1814 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1815 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1816 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1817 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1818
1819 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1820 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1821 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1822 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1823
1824 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1825 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1826
1827 pr_info("XgmiDpmPstates\n");
1828 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1829 pr_info(" .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1830 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1831 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1832
1833 pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1834 pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1835 pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1836 pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1837 pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1838 pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1839 pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1840 pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1841
1842 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1843 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1844 pptable->ReservedEquation0.a,
1845 pptable->ReservedEquation0.b,
1846 pptable->ReservedEquation0.c);
1847 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1848 pptable->ReservedEquation1.a,
1849 pptable->ReservedEquation1.b,
1850 pptable->ReservedEquation1.c);
1851 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1852 pptable->ReservedEquation2.a,
1853 pptable->ReservedEquation2.b,
1854 pptable->ReservedEquation2.c);
1855 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1856 pptable->ReservedEquation3.a,
1857 pptable->ReservedEquation3.b,
1858 pptable->ReservedEquation3.c);
1859
1860 pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1861 pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1862
1863 pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1864 pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1865 pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1866
1867 pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1868 pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1869
1870 pr_info("Board Parameters:\n");
1871 pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1872 pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1873
1874 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1875 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1876 pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1877 pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1878
1879 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1880 pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1881
1882 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1883 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1884 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1885
1886 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1887 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1888 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1889
1890 pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1891 pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1892 pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1893
1894 pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1895 pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1896 pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1897
1898 pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1899 pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1900 pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1901 pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1902
1903 pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1904 pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1905 pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1906
1907 pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1908 pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1909 pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1910
1911 pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1912 pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1913 pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1914
1915 pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1916 pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1917 pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1918
1919 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1920 pr_info("I2cControllers[%d]:\n", i);
1921 pr_info(" .Enabled = %d\n",
1922 pptable->I2cControllers[i].Enabled);
1923 pr_info(" .SlaveAddress = 0x%x\n",
1924 pptable->I2cControllers[i].SlaveAddress);
1925 pr_info(" .ControllerPort = %d\n",
1926 pptable->I2cControllers[i].ControllerPort);
1927 pr_info(" .ControllerName = %d\n",
1928 pptable->I2cControllers[i].ControllerName);
1929 pr_info(" .ThermalThrottler = %d\n",
1930 pptable->I2cControllers[i].ThermalThrotter);
1931 pr_info(" .I2cProtocol = %d\n",
1932 pptable->I2cControllers[i].I2cProtocol);
1933 pr_info(" .Speed = %d\n",
1934 pptable->I2cControllers[i].Speed);
1935 }
1936
1937 pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1938 pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1939
1940 pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1941
1942 pr_info("XgmiLinkSpeed\n");
1943 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1944 pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1945 pr_info("XgmiLinkWidth\n");
1946 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1947 pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1948 pr_info("XgmiFclkFreq\n");
1949 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1950 pr_info(" .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1951 pr_info("XgmiSocVoltage\n");
1952 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1953 pr_info(" .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1954
1955 }
1956
arcturus_is_dpm_running(struct smu_context * smu)1957 static bool arcturus_is_dpm_running(struct smu_context *smu)
1958 {
1959 int ret = 0;
1960 uint32_t feature_mask[2];
1961 unsigned long feature_enabled;
1962 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1963 if (ret)
1964 return false;
1965 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1966 ((uint64_t)feature_mask[1] << 32));
1967 return !!(feature_enabled & SMC_DPM_FEATURE);
1968 }
1969
arcturus_dpm_set_uvd_enable(struct smu_context * smu,bool enable)1970 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
1971 {
1972 struct smu_power_context *smu_power = &smu->smu_power;
1973 struct smu_power_gate *power_gate = &smu_power->power_gate;
1974 int ret = 0;
1975
1976 if (enable) {
1977 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1978 ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1979 if (ret) {
1980 pr_err("[EnableVCNDPM] failed!\n");
1981 return ret;
1982 }
1983 }
1984 power_gate->vcn_gated = false;
1985 } else {
1986 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1987 ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1988 if (ret) {
1989 pr_err("[DisableVCNDPM] failed!\n");
1990 return ret;
1991 }
1992 }
1993 power_gate->vcn_gated = true;
1994 }
1995
1996 return ret;
1997 }
1998
1999
arcturus_fill_eeprom_i2c_req(SwI2cRequest_t * req,bool write,uint8_t address,uint32_t numbytes,uint8_t * data)2000 static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t *req, bool write,
2001 uint8_t address, uint32_t numbytes,
2002 uint8_t *data)
2003 {
2004 int i;
2005
2006 BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
2007
2008 req->I2CcontrollerPort = 0;
2009 req->I2CSpeed = 2;
2010 req->SlaveAddress = address;
2011 req->NumCmds = numbytes;
2012
2013 for (i = 0; i < numbytes; i++) {
2014 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
2015
2016 /* First 2 bytes are always write for lower 2b EEPROM address */
2017 if (i < 2)
2018 cmd->Cmd = 1;
2019 else
2020 cmd->Cmd = write;
2021
2022
2023 /* Add RESTART for read after address filled */
2024 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2025
2026 /* Add STOP in the end */
2027 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2028
2029 /* Fill with data regardless if read or write to simplify code */
2030 cmd->RegisterAddr = data[i];
2031 }
2032 }
2033
arcturus_i2c_eeprom_read_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)2034 static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
2035 uint8_t address,
2036 uint8_t *data,
2037 uint32_t numbytes)
2038 {
2039 uint32_t i, ret = 0;
2040 SwI2cRequest_t req;
2041 struct amdgpu_device *adev = to_amdgpu_device(control);
2042 struct smu_table_context *smu_table = &adev->smu.smu_table;
2043 struct smu_table *table = &smu_table->driver_table;
2044
2045 memset(&req, 0, sizeof(req));
2046 arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
2047
2048 mutex_lock(&adev->smu.mutex);
2049 /* Now read data starting with that address */
2050 ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2051 true);
2052 mutex_unlock(&adev->smu.mutex);
2053
2054 if (!ret) {
2055 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2056
2057 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
2058 for (i = 0; i < numbytes; i++)
2059 data[i] = res->SwI2cCmds[i].Data;
2060
2061 pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
2062 (uint16_t)address, numbytes);
2063
2064 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2065 8, 1, data, numbytes, false);
2066 } else
2067 pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
2068
2069 return ret;
2070 }
2071
arcturus_i2c_eeprom_write_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)2072 static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
2073 uint8_t address,
2074 uint8_t *data,
2075 uint32_t numbytes)
2076 {
2077 uint32_t ret;
2078 SwI2cRequest_t req;
2079 struct amdgpu_device *adev = to_amdgpu_device(control);
2080
2081 memset(&req, 0, sizeof(req));
2082 arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
2083
2084 mutex_lock(&adev->smu.mutex);
2085 ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2086 mutex_unlock(&adev->smu.mutex);
2087
2088 if (!ret) {
2089 pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
2090 (uint16_t)address, numbytes);
2091
2092 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2093 8, 1, data, numbytes, false);
2094 /*
2095 * According to EEPROM spec there is a MAX of 10 ms required for
2096 * EEPROM to flush internal RX buffer after STOP was issued at the
2097 * end of write transaction. During this time the EEPROM will not be
2098 * responsive to any more commands - so wait a bit more.
2099 */
2100 msleep(10);
2101
2102 } else
2103 pr_err("arcturus_i2c_write- error occurred :%x", ret);
2104
2105 return ret;
2106 }
2107
arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,int num)2108 static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
2109 struct i2c_msg *msgs, int num)
2110 {
2111 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2112 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2113
2114 for (i = 0; i < num; i++) {
2115 /*
2116 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2117 * once and hence the data needs to be spliced into chunks and sent each
2118 * chunk separately
2119 */
2120 data_size = msgs[i].len - 2;
2121 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2122 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2123 data_ptr = msgs[i].buf + 2;
2124
2125 for (j = 0; j < data_size / data_chunk_size; j++) {
2126 /* Insert the EEPROM dest addess, bits 0-15 */
2127 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2128 data_chunk[1] = (next_eeprom_addr & 0xff);
2129
2130 if (msgs[i].flags & I2C_M_RD) {
2131 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2132 (uint8_t)msgs[i].addr,
2133 data_chunk, MAX_SW_I2C_COMMANDS);
2134
2135 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2136 } else {
2137
2138 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2139
2140 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2141 (uint8_t)msgs[i].addr,
2142 data_chunk, MAX_SW_I2C_COMMANDS);
2143 }
2144
2145 if (ret) {
2146 num = -EIO;
2147 goto fail;
2148 }
2149
2150 next_eeprom_addr += data_chunk_size;
2151 data_ptr += data_chunk_size;
2152 }
2153
2154 if (data_size % data_chunk_size) {
2155 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2156 data_chunk[1] = (next_eeprom_addr & 0xff);
2157
2158 if (msgs[i].flags & I2C_M_RD) {
2159 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2160 (uint8_t)msgs[i].addr,
2161 data_chunk, (data_size % data_chunk_size) + 2);
2162
2163 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2164 } else {
2165 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2166
2167 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2168 (uint8_t)msgs[i].addr,
2169 data_chunk, (data_size % data_chunk_size) + 2);
2170 }
2171
2172 if (ret) {
2173 num = -EIO;
2174 goto fail;
2175 }
2176 }
2177 }
2178
2179 fail:
2180 return num;
2181 }
2182
arcturus_i2c_eeprom_i2c_func(struct i2c_adapter * adap)2183 static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2184 {
2185 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2186 }
2187
2188
2189 static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2190 .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2191 .functionality = arcturus_i2c_eeprom_i2c_func,
2192 };
2193
arcturus_i2c_eeprom_control_init(struct i2c_adapter * control)2194 static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
2195 {
2196 struct amdgpu_device *adev = to_amdgpu_device(control);
2197 struct smu_context *smu = &adev->smu;
2198 int res;
2199
2200 if (!smu->pm_enabled)
2201 return -EOPNOTSUPP;
2202
2203 control->owner = THIS_MODULE;
2204 control->class = I2C_CLASS_SPD;
2205 #ifndef __NetBSD__
2206 control->dev.parent = &adev->pdev->dev;
2207 #endif
2208 control->algo = &arcturus_i2c_eeprom_i2c_algo;
2209 snprintf(control->name, sizeof(control->name), "RAS EEPROM");
2210
2211 res = i2c_add_adapter(control);
2212 if (res)
2213 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2214
2215 return res;
2216 }
2217
arcturus_i2c_eeprom_control_fini(struct i2c_adapter * control)2218 static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
2219 {
2220 struct amdgpu_device *adev = to_amdgpu_device(control);
2221 struct smu_context *smu = &adev->smu;
2222
2223 if (!smu->pm_enabled)
2224 return;
2225
2226 i2c_del_adapter(control);
2227 }
2228
arcturus_get_pptable_power_limit(struct smu_context * smu)2229 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
2230 {
2231 PPTable_t *pptable = smu->smu_table.driver_pptable;
2232
2233 return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2234 }
2235
2236 static const struct pptable_funcs arcturus_ppt_funcs = {
2237 /* translate smu index into arcturus specific index */
2238 .get_smu_msg_index = arcturus_get_smu_msg_index,
2239 .get_smu_clk_index = arcturus_get_smu_clk_index,
2240 .get_smu_feature_index = arcturus_get_smu_feature_index,
2241 .get_smu_table_index = arcturus_get_smu_table_index,
2242 .get_smu_power_index= arcturus_get_pwr_src_index,
2243 .get_workload_type = arcturus_get_workload_type,
2244 /* internal structurs allocations */
2245 .tables_init = arcturus_tables_init,
2246 .alloc_dpm_context = arcturus_allocate_dpm_context,
2247 /* pptable related */
2248 .check_powerplay_table = arcturus_check_powerplay_table,
2249 .store_powerplay_table = arcturus_store_powerplay_table,
2250 .append_powerplay_table = arcturus_append_powerplay_table,
2251 /* init dpm */
2252 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2253 /* btc */
2254 .run_btc = arcturus_run_btc,
2255 /* dpm/clk tables */
2256 .set_default_dpm_table = arcturus_set_default_dpm_table,
2257 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2258 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2259 .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
2260 .print_clk_levels = arcturus_print_clk_levels,
2261 .force_clk_levels = arcturus_force_clk_levels,
2262 .read_sensor = arcturus_read_sensor,
2263 .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2264 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2265 .force_dpm_limit_value = arcturus_force_dpm_limit_value,
2266 .unforce_dpm_levels = arcturus_unforce_dpm_levels,
2267 .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
2268 .get_power_profile_mode = arcturus_get_power_profile_mode,
2269 .set_power_profile_mode = arcturus_set_power_profile_mode,
2270 .set_performance_level = smu_v11_0_set_performance_level,
2271 /* debug (internal used) */
2272 .dump_pptable = arcturus_dump_pptable,
2273 .get_power_limit = arcturus_get_power_limit,
2274 .is_dpm_running = arcturus_is_dpm_running,
2275 .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
2276 .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2277 .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
2278 .init_microcode = smu_v11_0_init_microcode,
2279 .load_microcode = smu_v11_0_load_microcode,
2280 .init_smc_tables = smu_v11_0_init_smc_tables,
2281 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2282 .init_power = smu_v11_0_init_power,
2283 .fini_power = smu_v11_0_fini_power,
2284 .check_fw_status = smu_v11_0_check_fw_status,
2285 .setup_pptable = smu_v11_0_setup_pptable,
2286 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2287 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2288 .check_pptable = smu_v11_0_check_pptable,
2289 .parse_pptable = smu_v11_0_parse_pptable,
2290 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2291 .check_fw_version = smu_v11_0_check_fw_version,
2292 .write_pptable = smu_v11_0_write_pptable,
2293 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2294 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2295 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2296 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2297 .system_features_control = smu_v11_0_system_features_control,
2298 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2299 .read_smc_arg = smu_v11_0_read_arg,
2300 .init_display_count = smu_v11_0_init_display_count,
2301 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2302 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2303 .notify_display_change = smu_v11_0_notify_display_change,
2304 .set_power_limit = smu_v11_0_set_power_limit,
2305 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2306 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2307 .start_thermal_control = smu_v11_0_start_thermal_control,
2308 .stop_thermal_control = smu_v11_0_stop_thermal_control,
2309 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2310 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2311 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2312 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2313 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2314 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2315 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2316 .gfx_off_control = smu_v11_0_gfx_off_control,
2317 .register_irq_handler = smu_v11_0_register_irq_handler,
2318 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2319 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2320 .baco_is_support= smu_v11_0_baco_is_support,
2321 .baco_get_state = smu_v11_0_baco_get_state,
2322 .baco_set_state = smu_v11_0_baco_set_state,
2323 .baco_enter = smu_v11_0_baco_enter,
2324 .baco_exit = smu_v11_0_baco_exit,
2325 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2326 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2327 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2328 .get_pptable_power_limit = arcturus_get_pptable_power_limit,
2329 };
2330
arcturus_set_ppt_funcs(struct smu_context * smu)2331 void arcturus_set_ppt_funcs(struct smu_context *smu)
2332 {
2333 smu->ppt_funcs = &arcturus_ppt_funcs;
2334 }
2335