1 /* $NetBSD: mcontext.h,v 1.16 2024/11/30 01:04:09 christos Exp $ */ 2 3 #ifndef _HPPA_MCONTEXT_H_ 4 #define _HPPA_MCONTEXT_H_ 5 6 /* 7 * General register state 8 */ 9 #define _NGREG 44 10 11 #define _REG_R1 1 12 #define _REG_R2 2 13 #define _REG_R3 3 14 #define _REG_R4 4 15 #define _REG_R5 5 16 #define _REG_R6 6 17 #define _REG_R7 7 18 #define _REG_R8 8 19 #define _REG_R9 9 20 #define _REG_R10 10 21 #define _REG_R11 11 22 #define _REG_R12 12 23 #define _REG_R13 13 24 #define _REG_R14 14 25 #define _REG_R15 15 26 #define _REG_R16 16 27 #define _REG_R17 17 28 #define _REG_R18 18 29 #define _REG_R19 19 30 #define _REG_R20 20 31 #define _REG_R21 21 32 #define _REG_R22 22 33 #define _REG_R23 23 34 #define _REG_R24 24 35 #define _REG_R25 25 36 #define _REG_R26 26 37 #define _REG_R27 27 38 #define _REG_R28 28 39 #define _REG_R29 29 40 #define _REG_R30 30 41 #define _REG_R31 31 42 43 #define _REG_PSW 0 44 #define _REG_RP 2 45 #define _REG_R19 19 46 #define _REG_ARG0 26 47 #define _REG_DP 27 48 #define _REG_RET0 28 49 #define _REG_SP 30 50 #define _REG_SAR 32 51 #define _REG_PCSQH 33 52 #define _REG_PCSQT 34 53 #define _REG_PCOQH 35 54 #define _REG_PCOQT 36 55 #define _REG_SR0 37 56 #define _REG_SR1 38 57 #define _REG_SR2 39 58 #define _REG_SR3 40 59 #define _REG_SR4 41 60 #define _REG_CR26 42 61 #define _REG_CR27 43 62 63 #ifndef __ASSEMBLER__ 64 65 typedef unsigned long __greg_t; 66 typedef __greg_t __gregset_t[_NGREG]; 67 68 /* 69 * Floating point register state 70 */ 71 72 typedef struct { 73 union { 74 unsigned long long __fp_regs[32]; 75 double __fp_dregs[32]; 76 } __fp_fr; 77 } __fpregset_t; 78 79 typedef struct { 80 __gregset_t __gregs; 81 __fpregset_t __fpregs; 82 } mcontext_t; 83 84 #define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP]) 85 #define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[3]) 86 #define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_PCOQH]) 87 #define _UC_MACHINE_SET_PC(uc, pc) \ 88 do { \ 89 (uc)->uc_mcontext.__gregs[_REG_PCOQH] = (pc); \ 90 (uc)->uc_mcontext.__gregs[_REG_PCOQT] = (pc) + 4; \ 91 } while (/*CONSTCOND*/0) 92 #define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_RET0]) 93 94 #endif /* !__ASSEMBLER__ */ 95 96 #define _UC_SETSTACK _UC_MD_BIT16 97 #define _UC_CLRSTACK _UC_MD_BIT17 98 #define _UC_TLSBASE _UC_MD_BIT18 99 100 #endif /* _HPPA_MCONTEXT_H_ */ 101