1 /* $NetBSD: vireg.h,v 1.3 2024/10/13 16:21:37 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _WII_DEV_VIREG_H 30 #define _WII_DEV_VIREG_H 31 32 /* 33 * Nintendo Wii Video Interface (VI) registers, from 34 * https://www.gc-forever.com/yagcd/ 35 */ 36 37 /* [2B] VTR - Vertical Timing Register */ 38 #define VI_VTR 0x00 39 #define VI_VTR_ACV __BITS(13,4) 40 #define VI_VTR_EQU __BITS(3,0) 41 42 /* [2B] DCR - Display Configuration Register */ 43 #define VI_DCR 0x02 44 #define VI_DCR_FMT __BITS(9,8) 45 #define VI_DCR_FMT_NTSC 0 46 #define VI_DCR_FMT_PAL 1 47 #define VI_DCR_FMT_MPAL 2 48 #define VI_DCR_FMT_DEBUG 3 49 #define VI_DCR_LE1 __BITS(7,6) 50 #define VI_DCR_LE0 __BITS(5,4) 51 #define VI_DCR_DLR __BIT(3) 52 #define VI_DCR_NIN __BIT(2) 53 #define VI_DCR_RST __BIT(1) 54 #define VI_DCR_ENB __BIT(0) 55 56 /* [4B] HTR0 - Horizontal Timing 0 */ 57 #define VI_HTR0 0x04 58 #define VI_HTR0_HCS __BITS(30,24) 59 #define VI_HTR0_HCE __BITS(22,16) 60 #define VI_HTR0_HLW __BITS(8,0) 61 62 /* [4B] HTR1 - Horizontal Timing 1 */ 63 #define VI_HTR1 0x08 64 #define VI_HTR1_HBS __BITS(26,17) 65 #define VI_HTR1_HBE __BITS(16,7) 66 #define VI_HTR1_HSY __BITS(6,0) 67 68 /* [4B] VTO - Odd Field Vertical Timing Register */ 69 #define VI_VTO 0x0c 70 #define VI_VTO_PSB __BITS(25,16) 71 #define VI_VTO_PRB __BITS(9,0) 72 73 /* [4B] VTE - Even Field Vertical Timing Register */ 74 #define VI_VTE 0x10 75 #define VI_VTE_PSB __BITS(25,16) 76 #define VI_VTE_PRB __BITS(9,0) 77 78 /* [4B] BBOI - Odd Field Burst Blanking Interval Register */ 79 #define VI_BBOI 0x14 80 #define VI_BBOI_BE3 __BITS(31,21) 81 #define VI_BBOI_BS3 __BITS(20,16) 82 #define VI_BBOI_BE1 __BITS(15,5) 83 #define VI_BBOI_BS1 __BITS(4,0) 84 85 /* [4B] BBEI - Even Field Burst Blanking Interval Register */ 86 #define VI_BBEI 0x18 87 #define VI_BBEI_BE4 __BITS(31,21) 88 #define VI_BBEI_BS4 __BITS(20,16) 89 #define VI_BBEI_BE2 __BITS(15,5) 90 #define VI_BBEI_BS2 __BITS(4,0) 91 92 /* [4B] TFBL - Top Field Base Register (L) */ 93 #define VI_TFBL 0x1c 94 #define VI_TFBL_PGOFF __BIT(28) 95 #define VI_TFBL_XOF __BITS(27,24) 96 #define VI_TFBL_FBB __BITS(23,0) 97 98 /* [4B] TFBR - Top Field Base Register (R) */ 99 #define VI_TFBR 0x20 100 #define VI_TFBR_FBB __BITS(23,0) 101 102 /* [4B] BFBL - Bottom Field Base Register (L) */ 103 #define VI_BFBL 0x24 104 #define VI_BFBL_PGOFF __BIT(28) 105 #define VI_BFBL_XOF __BITS(27,24) 106 #define VI_BFBL_FBB __BITS(23,0) 107 108 /* [4B] BFBR - Bottom Field Base Register (R) */ 109 #define VI_BFBR 0x28 110 #define VI_BFBR_FBB __BITS(23,0) 111 112 /* [2B] DPV - Current Vertical Position */ 113 #define VI_DPV 0x2c 114 #define VI_DPV_VCT __BITS(10,0) 115 116 /* [2B] DPH - Current Horizontal Position */ 117 #define VI_DPH 0x2e 118 #define VI_DPH_HCT __BITS(10,0) 119 120 /* [4B] DI[0-3] - Display Interrupt 0-3 */ 121 #define VI_DI0 0x30 122 #define VI_DI1 0x34 123 #define VI_DI2 0x38 124 #define VI_DI3 0x3c 125 #define VI_DI_INT __BIT(31) 126 #define VI_DI_ENB __BIT(28) 127 #define VI_DI_VCT __BITS(25,16) 128 #define VI_DI_HCT __BITS(9,0) 129 130 /* [4B] DL[0-1] - Display Latch Register 0-1 */ 131 #define VI_DL0 0x40 132 #define VI_DL1 0x44 133 #define VI_DL_TRG __BIT(31) 134 #define VI_DL_VCT __BITS(26,16) 135 #define VI_DL_HCT __BITS(10,0) 136 137 /* [2B] PICCONF - Picture Configuration Register */ 138 #define VI_PICCONF 0x48 139 #define VI_PICCONF_READS __BITS(15,8) 140 #define VI_PICCONF_STRIDES __BITS(7,0) 141 142 /* [2B] HSR - Horizontal Scaling Register */ 143 #define VI_HSR 0x4a 144 #define VI_HSR_HS_EN __BIT(12) 145 #define VI_HSR_STP __BITS(8,0) 146 147 /* [4B] FCT[0-6] - Filter Coefficient Table 0-6 */ 148 #define VI_FCT0 0x4c 149 #define VI_FCT1 0x50 150 #define VI_FCT2 0x54 151 #define VI_FCT3 0x58 152 #define VI_FCT4 0x5c 153 #define VI_FCT5 0x60 154 #define VI_FCT6 0x64 155 156 /* [4B] ??? */ 157 #define VI_UNKNOWN_68H 0x68 158 159 /* [2B] VICLK - VI Clock Select Register */ 160 #define VI_VICLK 0x6c 161 #define VI_VICLK_SEL __BIT(0) 162 #define VI_VICLK_SEL_27MHZ 0 163 #define VI_VICLK_SEL_54MHZ 1 164 165 /* [2B] VISEL - VI DTV Status Register */ 166 #define VI_VISEL 0x6e 167 #define VI_VISEL_SEL __BIT(2) 168 #define VI_VISEL_COMPONENT_CABLE __BIT(0) 169 170 /* [2B] VI_HSCALINGW - Horizontal Scaling Width */ 171 #define VI_HSCALINGW 0x70 172 #define VI_HSCALINGW_WIDTH __BITS(9,0) 173 174 /* [2B] HBE - Border HBE */ 175 #define VI_HBE 0x72 176 #define VI_HBE_BRDR_EN __BIT(15) 177 #define VI_HBE_HBE656 __BITS(9,0) 178 179 /* [2B] HBS - Border HBS */ 180 #define VI_HBS 0x74 181 #define VI_HBS_HBS656 __BITS(9,0) 182 183 /* [2B] ??? */ 184 #define VI_UNKNOWN_76H 0x76 185 186 /* [4B] ??? */ 187 #define VI_UNKNOWN_78H 0x78 188 189 /* [4B] ??? */ 190 #define VI_UNKNOWN_7CH 0x7c 191 192 #endif /* !_WII_DEV_VIREG_H */ 193