1 /* $NetBSD: xlnx-zynqmp-clk.h,v 1.1.1.1 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Xilinx Zynq MPSoC Firmware layer 6 * 7 * Copyright (C) 2014-2018 Xilinx, Inc. 8 * 9 */ 10 11 #ifndef _DT_BINDINGS_CLK_ZYNQMP_H 12 #define _DT_BINDINGS_CLK_ZYNQMP_H 13 14 #define IOPLL 0 15 #define RPLL 1 16 #define APLL 2 17 #define DPLL 3 18 #define VPLL 4 19 #define IOPLL_TO_FPD 5 20 #define RPLL_TO_FPD 6 21 #define APLL_TO_LPD 7 22 #define DPLL_TO_LPD 8 23 #define VPLL_TO_LPD 9 24 #define ACPU 10 25 #define ACPU_HALF 11 26 #define DBF_FPD 12 27 #define DBF_LPD 13 28 #define DBG_TRACE 14 29 #define DBG_TSTMP 15 30 #define DP_VIDEO_REF 16 31 #define DP_AUDIO_REF 17 32 #define DP_STC_REF 18 33 #define GDMA_REF 19 34 #define DPDMA_REF 20 35 #define DDR_REF 21 36 #define SATA_REF 22 37 #define PCIE_REF 23 38 #define GPU_REF 24 39 #define GPU_PP0_REF 25 40 #define GPU_PP1_REF 26 41 #define TOPSW_MAIN 27 42 #define TOPSW_LSBUS 28 43 #define GTGREF0_REF 29 44 #define LPD_SWITCH 30 45 #define LPD_LSBUS 31 46 #define USB0_BUS_REF 32 47 #define USB1_BUS_REF 33 48 #define USB3_DUAL_REF 34 49 #define USB0 35 50 #define USB1 36 51 #define CPU_R5 37 52 #define CPU_R5_CORE 38 53 #define CSU_SPB 39 54 #define CSU_PLL 40 55 #define PCAP 41 56 #define IOU_SWITCH 42 57 #define GEM_TSU_REF 43 58 #define GEM_TSU 44 59 #define GEM0_TX 45 60 #define GEM1_TX 46 61 #define GEM2_TX 47 62 #define GEM3_TX 48 63 #define GEM0_RX 49 64 #define GEM1_RX 50 65 #define GEM2_RX 51 66 #define GEM3_RX 52 67 #define QSPI_REF 53 68 #define SDIO0_REF 54 69 #define SDIO1_REF 55 70 #define UART0_REF 56 71 #define UART1_REF 57 72 #define SPI0_REF 58 73 #define SPI1_REF 59 74 #define NAND_REF 60 75 #define I2C0_REF 61 76 #define I2C1_REF 62 77 #define CAN0_REF 63 78 #define CAN1_REF 64 79 #define CAN0 65 80 #define CAN1 66 81 #define DLL_REF 67 82 #define ADMA_REF 68 83 #define TIMESTAMP_REF 69 84 #define AMS_REF 70 85 #define PL0_REF 71 86 #define PL1_REF 72 87 #define PL2_REF 73 88 #define PL3_REF 74 89 #define WDT 75 90 #define IOPLL_INT 76 91 #define IOPLL_PRE_SRC 77 92 #define IOPLL_HALF 78 93 #define IOPLL_INT_MUX 79 94 #define IOPLL_POST_SRC 80 95 #define RPLL_INT 81 96 #define RPLL_PRE_SRC 82 97 #define RPLL_HALF 83 98 #define RPLL_INT_MUX 84 99 #define RPLL_POST_SRC 85 100 #define APLL_INT 86 101 #define APLL_PRE_SRC 87 102 #define APLL_HALF 88 103 #define APLL_INT_MUX 89 104 #define APLL_POST_SRC 90 105 #define DPLL_INT 91 106 #define DPLL_PRE_SRC 92 107 #define DPLL_HALF 93 108 #define DPLL_INT_MUX 94 109 #define DPLL_POST_SRC 95 110 #define VPLL_INT 96 111 #define VPLL_PRE_SRC 97 112 #define VPLL_HALF 98 113 #define VPLL_INT_MUX 99 114 #define VPLL_POST_SRC 100 115 #define CAN0_MIO 101 116 #define CAN1_MIO 102 117 #define ACPU_FULL 103 118 #define GEM0_REF 104 119 #define GEM1_REF 105 120 #define GEM2_REF 106 121 #define GEM3_REF 107 122 #define GEM0_REF_UNG 108 123 #define GEM1_REF_UNG 109 124 #define GEM2_REF_UNG 110 125 #define GEM3_REF_UNG 111 126 #define LPD_WDT 112 127 128 #endif 129