xref: /netbsd-src/sys/arch/arm/ep93xx/epclkreg.h (revision 7804a487ed1c65ca40d4dd472f0ab80f0e4d1b02)
1 /*	$NetBSD: epclkreg.h,v 1.4 2021/11/21 08:25:26 skrll Exp $ */
2 
3 /*
4  * Copyright (c) 2004 Jesse Off
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
16  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
19  * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
20  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
25  * THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 
29 #ifndef _EPCLKREG_H_
30 #define _EPCLKREG_H_
31 
32 /* Timer1 16-bit timer (Free running/Load based) */
33 #define	EP93XX_TIMERS_Timer1Load	0x00000000UL
34 #define	 TimerLoad_MASK			0x0000ffffUL
35 #define	EP93XX_TIMERS_Timer1Value	0x00000004UL
36 #define	 TimerValue_MASK		0x0000ffffUL
37 #define	EP93XX_TIMERS_Timer1Control	0x00000008UL
38 #define	 TimerControl_ENABLE		(1<<7)
39 #define	 TimerControl_MODE		(1<<6)
40 #define	 TimerControl_CLKSEL		(1<<3)
41 #define	EP93XX_TIMERS_Timer1Clear	0x0000000cUL
42 
43 /* Timer2 16-bit timer (Free running/Load based) */
44 #define	EP93XX_TIMERS_Timer2Load	0x00000020UL
45 #define	EP93XX_TIMERS_Timer2Value	0x00000024UL
46 #define	EP93XX_TIMERS_Timer2Control	0x00000028UL
47 #define	EP93XX_TIMERS_Timer2Clear	0x0000002cUL
48 
49 /* Timer3 32-bit timer (Free running/Load based) */
50 #define	EP93XX_TIMERS_Timer3Load	0x00000080UL
51 #define	EP93XX_TIMERS_Timer3Value	0x00000084UL
52 #define	EP93XX_TIMERS_Timer3Control	0x00000088UL
53 #define	EP93XX_TIMERS_Timer3Clear	0x0000008cUL
54 
55 /* Timer4 40-bit timer (Free running) */
56 #define	EP93XX_TIMERS_Timer4Enable	0x00000064UL
57 #define	EP93XX_TIMERS_Timer4ValueHigh	0x00000064UL
58 #define	EP93XX_TIMERS_Timer4ValueLow	0x00000060UL
59 
60 #endif /* _EPCLKREG_H_ */
61