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Searched defs:SubReg1 (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp207 unsigned SubReg1; in isProfitableToTransform() local
299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
H A DAArch64ISelLowering.cpp16612 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32); in createGPRPairNode() local
16660 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; in ReplaceCMP_SWAP_128Results() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1834 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1845 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1856 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1867 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1879 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode() local
1894 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createQuadDRegsNode() local
1909 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQuadQRegsNode() local
H A DARMISelLowering.cpp9764 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp188 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp780 SDValue RC, SubReg0, SubReg1; in Select() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1172 unsigned SubReg1 = MI.getOperand(1).getSubReg(); in commuteInstructionImpl() local