Searched defs:SubReg0 (Results 1 – 7 of 7) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 206 unsigned SubReg0; in isProfitableToTransform() local
298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
|
| H A D | AArch64ISelLowering.cpp | 16611 SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, dl, MVT::i32); in createGPRPairNode() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1833 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
1844 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode() local
1855 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode() local
1866 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode() local
1878 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createQuadSRegsNode() local
1893 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createQuadDRegsNode() local
1908 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQuadQRegsNode() local
|
| H A D | ARMISelLowering.cpp | 9763 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 187 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 68 unsigned RegClassID, unsigned SubReg0) { in createTupleImpl()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 780 SDValue RC, SubReg0, SubReg1; in Select() local
|