1 //===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the function that parses the machine instructions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_MIRPARSER_MIPARSER_H 14 #define LLVM_CODEGEN_MIRPARSER_MIPARSER_H 15 16 #include "llvm/ADT/DenseMap.h" 17 #include "llvm/ADT/StringMap.h" 18 #include "llvm/CodeGen/MachineMemOperand.h" 19 #include "llvm/CodeGen/Register.h" 20 #include "llvm/IR/TrackingMDRef.h" 21 #include "llvm/Support/Allocator.h" 22 #include "llvm/Support/SMLoc.h" 23 #include <map> 24 #include <utility> 25 26 namespace llvm { 27 28 class MachineBasicBlock; 29 class MachineFunction; 30 class MDNode; 31 class RegisterBank; 32 struct SlotMapping; 33 class SMDiagnostic; 34 class SourceMgr; 35 class StringRef; 36 class TargetRegisterClass; 37 class TargetSubtargetInfo; 38 39 struct VRegInfo { 40 enum : uint8_t { UNKNOWN, NORMAL, GENERIC, REGBANK } Kind = UNKNOWN; 41 bool Explicit = false; ///< VReg was explicitly specified in the .mir file. 42 union { 43 const TargetRegisterClass *RC; 44 const RegisterBank *RegBank; 45 } D; 46 Register VReg; 47 Register PreferredReg; 48 uint8_t Flags = 0; 49 }; 50 51 using Name2RegClassMap = StringMap<const TargetRegisterClass *>; 52 using Name2RegBankMap = StringMap<const RegisterBank *>; 53 54 struct PerTargetMIParsingState { 55 private: 56 const TargetSubtargetInfo &Subtarget; 57 58 /// Maps from instruction names to op codes. 59 StringMap<unsigned> Names2InstrOpCodes; 60 61 /// Maps from register names to registers. 62 StringMap<Register> Names2Regs; 63 64 /// Maps from register mask names to register masks. 65 StringMap<const uint32_t *> Names2RegMasks; 66 67 /// Maps from subregister names to subregister indices. 68 StringMap<unsigned> Names2SubRegIndices; 69 70 /// Maps from target index names to target indices. 71 StringMap<int> Names2TargetIndices; 72 73 /// Maps from direct target flag names to the direct target flag values. 74 StringMap<unsigned> Names2DirectTargetFlags; 75 76 /// Maps from direct target flag names to the bitmask target flag values. 77 StringMap<unsigned> Names2BitmaskTargetFlags; 78 79 /// Maps from MMO target flag names to MMO target flag values. 80 StringMap<MachineMemOperand::Flags> Names2MMOTargetFlags; 81 82 /// Maps from register class names to register classes. 83 Name2RegClassMap Names2RegClasses; 84 85 /// Maps from register bank names to register banks. 86 Name2RegBankMap Names2RegBanks; 87 88 void initNames2InstrOpCodes(); 89 void initNames2Regs(); 90 void initNames2RegMasks(); 91 void initNames2SubRegIndices(); 92 void initNames2TargetIndices(); 93 void initNames2DirectTargetFlags(); 94 void initNames2BitmaskTargetFlags(); 95 void initNames2MMOTargetFlags(); 96 97 void initNames2RegClasses(); 98 void initNames2RegBanks(); 99 100 public: 101 /// Try to convert an instruction name to an opcode. Return true if the 102 /// instruction name is invalid. 103 bool parseInstrName(StringRef InstrName, unsigned &OpCode); 104 105 /// Try to convert a register name to a register number. Return true if the 106 /// register name is invalid. 107 bool getRegisterByName(StringRef RegName, Register &Reg); 108 109 /// Check if the given identifier is a name of a register mask. 110 /// 111 /// Return null if the identifier isn't a register mask. 112 const uint32_t *getRegMask(StringRef Identifier); 113 114 /// Check if the given identifier is a name of a subregister index. 115 /// 116 /// Return 0 if the name isn't a subregister index class. 117 unsigned getSubRegIndex(StringRef Name); 118 119 /// Try to convert a name of target index to the corresponding target index. 120 /// 121 /// Return true if the name isn't a name of a target index. 122 bool getTargetIndex(StringRef Name, int &Index); 123 124 /// Try to convert a name of a direct target flag to the corresponding 125 /// target flag. 126 /// 127 /// Return true if the name isn't a name of a direct flag. 128 bool getDirectTargetFlag(StringRef Name, unsigned &Flag); 129 130 /// Try to convert a name of a bitmask target flag to the corresponding 131 /// target flag. 132 /// 133 /// Return true if the name isn't a name of a bitmask target flag. 134 bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag); 135 136 /// Try to convert a name of a MachineMemOperand target flag to the 137 /// corresponding target flag. 138 /// 139 /// Return true if the name isn't a name of a target MMO flag. 140 bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag); 141 142 /// Check if the given identifier is a name of a register class. 143 /// 144 /// Return null if the name isn't a register class. 145 const TargetRegisterClass *getRegClass(StringRef Name); 146 147 /// Check if the given identifier is a name of a register bank. 148 /// 149 /// Return null if the name isn't a register bank. 150 const RegisterBank *getRegBank(StringRef Name); 151 152 bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const; 153 154 PerTargetMIParsingState(const TargetSubtargetInfo &STI) 155 : Subtarget(STI) { 156 initNames2RegClasses(); 157 initNames2RegBanks(); 158 } 159 160 ~PerTargetMIParsingState() = default; 161 162 void setTarget(const TargetSubtargetInfo &NewSubtarget); 163 }; 164 165 struct PerFunctionMIParsingState { 166 BumpPtrAllocator Allocator; 167 MachineFunction &MF; 168 SourceMgr *SM; 169 const SlotMapping &IRSlots; 170 PerTargetMIParsingState &Target; 171 172 std::map<unsigned, TrackingMDNodeRef> MachineMetadataNodes; 173 std::map<unsigned, std::pair<TempMDTuple, SMLoc>> MachineForwardRefMDNodes; 174 175 DenseMap<unsigned, MachineBasicBlock *> MBBSlots; 176 DenseMap<Register, VRegInfo *> VRegInfos; 177 StringMap<VRegInfo *> VRegInfosNamed; 178 DenseMap<unsigned, int> FixedStackObjectSlots; 179 DenseMap<unsigned, int> StackObjectSlots; 180 DenseMap<unsigned, unsigned> ConstantPoolSlots; 181 DenseMap<unsigned, unsigned> JumpTableSlots; 182 183 /// Maps from slot numbers to function's unnamed values. 184 DenseMap<unsigned, const Value *> Slots2Values; 185 186 PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, 187 const SlotMapping &IRSlots, 188 PerTargetMIParsingState &Target); 189 190 VRegInfo &getVRegInfo(Register Num); 191 VRegInfo &getVRegInfoNamed(StringRef RegName); 192 const Value *getIRValue(unsigned Slot); 193 }; 194 195 /// Parse the machine basic block definitions, and skip the machine 196 /// instructions. 197 /// 198 /// This function runs the first parsing pass on the machine function's body. 199 /// It parses only the machine basic block definitions and creates the machine 200 /// basic blocks in the given machine function. 201 /// 202 /// The machine instructions aren't parsed during the first pass because all 203 /// the machine basic blocks aren't defined yet - this makes it impossible to 204 /// resolve the machine basic block references. 205 /// 206 /// Return true if an error occurred. 207 bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, 208 StringRef Src, SMDiagnostic &Error); 209 210 /// Parse the machine instructions. 211 /// 212 /// This function runs the second parsing pass on the machine function's body. 213 /// It skips the machine basic block definitions and parses only the machine 214 /// instructions and basic block attributes like liveins and successors. 215 /// 216 /// The second parsing pass assumes that the first parsing pass already ran 217 /// on the given source string. 218 /// 219 /// Return true if an error occurred. 220 bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, 221 SMDiagnostic &Error); 222 223 bool parseMBBReference(PerFunctionMIParsingState &PFS, 224 MachineBasicBlock *&MBB, StringRef Src, 225 SMDiagnostic &Error); 226 227 bool parseRegisterReference(PerFunctionMIParsingState &PFS, 228 Register &Reg, StringRef Src, 229 SMDiagnostic &Error); 230 231 bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, 232 StringRef Src, SMDiagnostic &Error); 233 234 bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, 235 VRegInfo *&Info, StringRef Src, 236 SMDiagnostic &Error); 237 238 bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, 239 StringRef Src, SMDiagnostic &Error); 240 241 bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, 242 SMDiagnostic &Error); 243 244 bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, 245 SMRange SourceRange, SMDiagnostic &Error); 246 247 } // end namespace llvm 248 249 #endif // LLVM_CODEGEN_MIRPARSER_MIPARSER_H 250