1 //===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone enum definitions for the RISC-V target 10 // useful for the compiler back-end and the MC libraries. 11 // 12 //===----------------------------------------------------------------------===// 13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H 14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H 15 16 #include "MCTargetDesc/RISCVMCTargetDesc.h" 17 #include "llvm/ADT/APFloat.h" 18 #include "llvm/ADT/APInt.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/TargetParser/RISCVISAInfo.h" 23 #include "llvm/TargetParser/RISCVTargetParser.h" 24 #include "llvm/TargetParser/SubtargetFeature.h" 25 26 namespace llvm { 27 28 // RISCVII - This namespace holds all of the target specific flags that 29 // instruction info tracks. All definitions must match RISCVInstrFormats.td. 30 namespace RISCVII { 31 enum { 32 InstFormatPseudo = 0, 33 InstFormatR = 1, 34 InstFormatR4 = 2, 35 InstFormatI = 3, 36 InstFormatS = 4, 37 InstFormatB = 5, 38 InstFormatU = 6, 39 InstFormatJ = 7, 40 InstFormatCR = 8, 41 InstFormatCI = 9, 42 InstFormatCSS = 10, 43 InstFormatCIW = 11, 44 InstFormatCL = 12, 45 InstFormatCS = 13, 46 InstFormatCA = 14, 47 InstFormatCB = 15, 48 InstFormatCJ = 16, 49 InstFormatCU = 17, 50 InstFormatCLB = 18, 51 InstFormatCLH = 19, 52 InstFormatCSB = 20, 53 InstFormatCSH = 21, 54 InstFormatOther = 22, 55 56 InstFormatMask = 31, 57 InstFormatShift = 0, 58 59 ConstraintShift = InstFormatShift + 5, 60 VS2Constraint = 0b001 << ConstraintShift, 61 VS1Constraint = 0b010 << ConstraintShift, 62 VMConstraint = 0b100 << ConstraintShift, 63 ConstraintMask = 0b111 << ConstraintShift, 64 65 VLMulShift = ConstraintShift + 3, 66 VLMulMask = 0b111 << VLMulShift, 67 68 // Force a tail agnostic policy even this instruction has a tied destination. 69 ForceTailAgnosticShift = VLMulShift + 3, 70 ForceTailAgnosticMask = 1 << ForceTailAgnosticShift, 71 72 // Is this a _TIED vector pseudo instruction. For these instructions we 73 // shouldn't skip the tied operand when converting to MC instructions. 74 IsTiedPseudoShift = ForceTailAgnosticShift + 1, 75 IsTiedPseudoMask = 1 << IsTiedPseudoShift, 76 77 // Does this instruction have a SEW operand. It will be the last explicit 78 // operand unless there is a vector policy operand. Used by RVV Pseudos. 79 HasSEWOpShift = IsTiedPseudoShift + 1, 80 HasSEWOpMask = 1 << HasSEWOpShift, 81 82 // Does this instruction have a VL operand. It will be the second to last 83 // explicit operand unless there is a vector policy operand. Used by RVV 84 // Pseudos. 85 HasVLOpShift = HasSEWOpShift + 1, 86 HasVLOpMask = 1 << HasVLOpShift, 87 88 // Does this instruction have a vector policy operand. It will be the last 89 // explicit operand. Used by RVV Pseudos. 90 HasVecPolicyOpShift = HasVLOpShift + 1, 91 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift, 92 93 // Is this instruction a vector widening reduction instruction. Used by RVV 94 // Pseudos. 95 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1, 96 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift, 97 98 // Does this instruction care about mask policy. If it is not, the mask policy 99 // could be either agnostic or undisturbed. For example, unmasked, store, and 100 // reduction operations result would not be affected by mask policy, so 101 // compiler has free to select either one. 102 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1, 103 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift, 104 105 // Indicates that the result can be considered sign extended from bit 31. Some 106 // instructions with this flag aren't W instructions, but are either sign 107 // extended from a smaller size, always outputs a small integer, or put zeros 108 // in bits 63:31. Used by the SExtWRemoval pass. 109 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1, 110 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift, 111 112 HasRoundModeOpShift = IsSignExtendingOpWShift + 1, 113 HasRoundModeOpMask = 1 << HasRoundModeOpShift, 114 115 UsesVXRMShift = HasRoundModeOpShift + 1, 116 UsesVXRMMask = 1 << UsesVXRMShift, 117 118 // Indicates whether these instructions can partially overlap between source 119 // registers and destination registers according to the vector spec. 120 // 0 -> not a vector pseudo 121 // 1 -> default value for vector pseudos. not widening or narrowing. 122 // 2 -> narrowing case 123 // 3 -> widening case 124 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1, 125 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift, 126 127 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2, 128 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift, 129 130 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1, 131 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift, 132 133 // Indicates the EEW of a vector instruction's destination operand. 134 // 0 -> 1 135 // 1 -> SEW 136 // 2 -> SEW * 2 137 // 3 -> SEW * 4 138 DestEEWShift = ElementsDependOnMaskShift + 1, 139 DestEEWMask = 3ULL << DestEEWShift, 140 }; 141 142 // Helper functions to read TSFlags. 143 /// \returns the format of the instruction. 144 static inline unsigned getFormat(uint64_t TSFlags) { 145 return (TSFlags & InstFormatMask) >> InstFormatShift; 146 } 147 /// \returns the LMUL for the instruction. 148 static inline VLMUL getLMul(uint64_t TSFlags) { 149 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift); 150 } 151 /// \returns true if tail agnostic is enforced for the instruction. 152 static inline bool doesForceTailAgnostic(uint64_t TSFlags) { 153 return TSFlags & ForceTailAgnosticMask; 154 } 155 /// \returns true if this a _TIED pseudo. 156 static inline bool isTiedPseudo(uint64_t TSFlags) { 157 return TSFlags & IsTiedPseudoMask; 158 } 159 /// \returns true if there is a SEW operand for the instruction. 160 static inline bool hasSEWOp(uint64_t TSFlags) { 161 return TSFlags & HasSEWOpMask; 162 } 163 /// \returns true if there is a VL operand for the instruction. 164 static inline bool hasVLOp(uint64_t TSFlags) { 165 return TSFlags & HasVLOpMask; 166 } 167 /// \returns true if there is a vector policy operand for this instruction. 168 static inline bool hasVecPolicyOp(uint64_t TSFlags) { 169 return TSFlags & HasVecPolicyOpMask; 170 } 171 /// \returns true if it is a vector widening reduction instruction. 172 static inline bool isRVVWideningReduction(uint64_t TSFlags) { 173 return TSFlags & IsRVVWideningReductionMask; 174 } 175 /// \returns true if mask policy is valid for the instruction. 176 static inline bool usesMaskPolicy(uint64_t TSFlags) { 177 return TSFlags & UsesMaskPolicyMask; 178 } 179 180 /// \returns true if there is a rounding mode operand for this instruction 181 static inline bool hasRoundModeOp(uint64_t TSFlags) { 182 return TSFlags & HasRoundModeOpMask; 183 } 184 185 /// \returns true if this instruction uses vxrm 186 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; } 187 188 /// \returns true if the elements in the body are affected by VL, 189 /// e.g. vslide1down.vx/vredsum.vs/viota.m 190 static inline bool elementsDependOnVL(uint64_t TSFlags) { 191 return TSFlags & ElementsDependOnVLMask; 192 } 193 194 /// \returns true if the elements in the body are affected by the mask, 195 /// e.g. vredsum.vs/viota.m 196 static inline bool elementsDependOnMask(uint64_t TSFlags) { 197 return TSFlags & ElementsDependOnMaskMask; 198 } 199 200 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) { 201 const uint64_t TSFlags = Desc.TSFlags; 202 // This method is only called if we expect to have a VL operand, and all 203 // instructions with VL also have SEW. 204 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags)); 205 unsigned Offset = 2; 206 if (hasVecPolicyOp(TSFlags)) 207 Offset = 3; 208 return Desc.getNumOperands() - Offset; 209 } 210 211 static inline unsigned getTailExpandUseRegNo(const FeatureBitset &FeatureBits) { 212 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch. 213 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL. 214 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6; 215 } 216 217 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) { 218 const uint64_t TSFlags = Desc.TSFlags; 219 assert(hasSEWOp(TSFlags)); 220 unsigned Offset = 1; 221 if (hasVecPolicyOp(TSFlags)) 222 Offset = 2; 223 return Desc.getNumOperands() - Offset; 224 } 225 226 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) { 227 assert(hasVecPolicyOp(Desc.TSFlags)); 228 return Desc.getNumOperands() - 1; 229 } 230 231 /// \returns the index to the rounding mode immediate value if any, otherwise 232 /// returns -1. 233 static inline int getFRMOpNum(const MCInstrDesc &Desc) { 234 const uint64_t TSFlags = Desc.TSFlags; 235 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags)) 236 return -1; 237 238 // The operand order 239 // -------------------------------------- 240 // | n-1 (if any) | n-2 | n-3 | n-4 | 241 // | policy | sew | vl | frm | 242 // -------------------------------------- 243 return getVLOpNum(Desc) - 1; 244 } 245 246 /// \returns the index to the rounding mode immediate value if any, otherwise 247 /// returns -1. 248 static inline int getVXRMOpNum(const MCInstrDesc &Desc) { 249 const uint64_t TSFlags = Desc.TSFlags; 250 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags)) 251 return -1; 252 // The operand order 253 // -------------------------------------- 254 // | n-1 (if any) | n-2 | n-3 | n-4 | 255 // | policy | sew | vl | vxrm | 256 // -------------------------------------- 257 return getVLOpNum(Desc) - 1; 258 } 259 260 // Is the first def operand tied to the first use operand. This is true for 261 // vector pseudo instructions that have a merge operand for tail/mask 262 // undisturbed. It's also true for vector FMA instructions where one of the 263 // operands is also the destination register. 264 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) { 265 return Desc.getNumDefs() < Desc.getNumOperands() && 266 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0; 267 } 268 269 // RISC-V Specific Machine Operand Flags 270 enum { 271 MO_None = 0, 272 MO_CALL = 1, 273 MO_LO = 3, 274 MO_HI = 4, 275 MO_PCREL_LO = 5, 276 MO_PCREL_HI = 6, 277 MO_GOT_HI = 7, 278 MO_TPREL_LO = 8, 279 MO_TPREL_HI = 9, 280 MO_TPREL_ADD = 10, 281 MO_TLS_GOT_HI = 11, 282 MO_TLS_GD_HI = 12, 283 MO_TLSDESC_HI = 13, 284 MO_TLSDESC_LOAD_LO = 14, 285 MO_TLSDESC_ADD_LO = 15, 286 MO_TLSDESC_CALL = 16, 287 288 // Used to differentiate between target-specific "direct" flags and "bitmask" 289 // flags. A machine operand can only have one "direct" flag, but can have 290 // multiple "bitmask" flags. 291 MO_DIRECT_FLAG_MASK = 31 292 }; 293 } // namespace RISCVII 294 295 namespace RISCVOp { 296 enum OperandType : unsigned { 297 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, 298 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM, 299 OPERAND_UIMM2, 300 OPERAND_UIMM2_LSB0, 301 OPERAND_UIMM3, 302 OPERAND_UIMM4, 303 OPERAND_UIMM5, 304 OPERAND_UIMM5_NONZERO, 305 OPERAND_UIMM5_GT3, 306 OPERAND_UIMM5_LSB0, 307 OPERAND_UIMM6, 308 OPERAND_UIMM6_LSB0, 309 OPERAND_UIMM7, 310 OPERAND_UIMM7_LSB00, 311 OPERAND_UIMM7_LSB000, 312 OPERAND_UIMM8_LSB00, 313 OPERAND_UIMM8, 314 OPERAND_UIMM8_LSB000, 315 OPERAND_UIMM8_GE32, 316 OPERAND_UIMM9_LSB000, 317 OPERAND_UIMM10, 318 OPERAND_UIMM10_LSB00_NONZERO, 319 OPERAND_UIMM11, 320 OPERAND_UIMM12, 321 OPERAND_UIMM16, 322 OPERAND_UIMM20, 323 OPERAND_UIMMLOG2XLEN, 324 OPERAND_UIMMLOG2XLEN_NONZERO, 325 OPERAND_UIMM32, 326 OPERAND_UIMM48, 327 OPERAND_UIMM64, 328 OPERAND_ZERO, 329 OPERAND_SIMM5, 330 OPERAND_SIMM5_PLUS1, 331 OPERAND_SIMM6, 332 OPERAND_SIMM6_NONZERO, 333 OPERAND_SIMM10_LSB0000_NONZERO, 334 OPERAND_SIMM12, 335 OPERAND_SIMM12_LSB00000, 336 OPERAND_SIMM26, 337 OPERAND_CLUI_IMM, 338 OPERAND_VTYPEI10, 339 OPERAND_VTYPEI11, 340 OPERAND_RVKRNUM, 341 OPERAND_RVKRNUM_0_7, 342 OPERAND_RVKRNUM_1_10, 343 OPERAND_RVKRNUM_2_14, 344 OPERAND_SPIMM, 345 // Operand is a 3-bit rounding mode, '111' indicates FRM register. 346 // Represents 'frm' argument passing to floating-point operations. 347 OPERAND_FRMARG, 348 // Operand is a 3-bit rounding mode where only RTZ is valid. 349 OPERAND_RTZARG, 350 // Condition code used by select and short forward branch pseudos. 351 OPERAND_COND_CODE, 352 // Vector policy operand. 353 OPERAND_VEC_POLICY, 354 // Vector SEW operand. Stores in log2(SEW). 355 OPERAND_SEW, 356 // Special SEW for mask only instructions. Always 0. 357 OPERAND_SEW_MASK, 358 // Vector rounding mode for VXRM or FRM. 359 OPERAND_VEC_RM, 360 OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM, 361 // Operand is either a register or uimm5, this is used by V extension pseudo 362 // instructions to represent a value that be passed as AVL to either vsetvli 363 // or vsetivli. 364 OPERAND_AVL, 365 }; 366 } // namespace RISCVOp 367 368 // Describes the predecessor/successor bits used in the FENCE instruction. 369 namespace RISCVFenceField { 370 enum FenceField { 371 I = 8, 372 O = 4, 373 R = 2, 374 W = 1 375 }; 376 } 377 378 // Describes the supported floating point rounding mode encodings. 379 namespace RISCVFPRndMode { 380 enum RoundingMode { 381 RNE = 0, 382 RTZ = 1, 383 RDN = 2, 384 RUP = 3, 385 RMM = 4, 386 DYN = 7, 387 Invalid 388 }; 389 390 inline static StringRef roundingModeToString(RoundingMode RndMode) { 391 switch (RndMode) { 392 default: 393 llvm_unreachable("Unknown floating point rounding mode"); 394 case RISCVFPRndMode::RNE: 395 return "rne"; 396 case RISCVFPRndMode::RTZ: 397 return "rtz"; 398 case RISCVFPRndMode::RDN: 399 return "rdn"; 400 case RISCVFPRndMode::RUP: 401 return "rup"; 402 case RISCVFPRndMode::RMM: 403 return "rmm"; 404 case RISCVFPRndMode::DYN: 405 return "dyn"; 406 } 407 } 408 409 inline static RoundingMode stringToRoundingMode(StringRef Str) { 410 return StringSwitch<RoundingMode>(Str) 411 .Case("rne", RISCVFPRndMode::RNE) 412 .Case("rtz", RISCVFPRndMode::RTZ) 413 .Case("rdn", RISCVFPRndMode::RDN) 414 .Case("rup", RISCVFPRndMode::RUP) 415 .Case("rmm", RISCVFPRndMode::RMM) 416 .Case("dyn", RISCVFPRndMode::DYN) 417 .Default(RISCVFPRndMode::Invalid); 418 } 419 420 inline static bool isValidRoundingMode(unsigned Mode) { 421 switch (Mode) { 422 default: 423 return false; 424 case RISCVFPRndMode::RNE: 425 case RISCVFPRndMode::RTZ: 426 case RISCVFPRndMode::RDN: 427 case RISCVFPRndMode::RUP: 428 case RISCVFPRndMode::RMM: 429 case RISCVFPRndMode::DYN: 430 return true; 431 } 432 } 433 } // namespace RISCVFPRndMode 434 435 namespace RISCVVXRndMode { 436 enum RoundingMode { 437 RNU = 0, 438 RNE = 1, 439 RDN = 2, 440 ROD = 3, 441 }; 442 } // namespace RISCVVXRndMode 443 444 //===----------------------------------------------------------------------===// 445 // Floating-point Immediates 446 // 447 448 namespace RISCVLoadFPImm { 449 float getFPImm(unsigned Imm); 450 451 /// getLoadFPImm - Return a 5-bit binary encoding of the floating-point 452 /// immediate value. If the value cannot be represented as a 5-bit binary 453 /// encoding, then return -1. 454 int getLoadFPImm(APFloat FPImm); 455 } // namespace RISCVLoadFPImm 456 457 namespace RISCVSysReg { 458 struct SysReg { 459 const char Name[32]; 460 unsigned Encoding; 461 // FIXME: add these additional fields when needed. 462 // Privilege Access: Read, Write, Read-Only. 463 // unsigned ReadWrite; 464 // Privilege Mode: User, System or Machine. 465 // unsigned Mode; 466 // Check field name. 467 // unsigned Extra; 468 // Register number without the privilege bits. 469 // unsigned Number; 470 FeatureBitset FeaturesRequired; 471 bool IsRV32Only; 472 bool IsAltName; 473 bool IsDeprecatedName; 474 475 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const { 476 // Not in 32-bit mode. 477 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit]) 478 return false; 479 // No required feature associated with the system register. 480 if (FeaturesRequired.none()) 481 return true; 482 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 483 } 484 }; 485 486 #define GET_SysRegEncodings_DECL 487 #define GET_SysRegsList_DECL 488 #include "RISCVGenSearchableTables.inc" 489 } // end namespace RISCVSysReg 490 491 namespace RISCVInsnOpcode { 492 struct RISCVOpcode { 493 const char *Name; 494 unsigned Value; 495 }; 496 497 #define GET_RISCVOpcodesList_DECL 498 #include "RISCVGenSearchableTables.inc" 499 } // end namespace RISCVInsnOpcode 500 501 namespace RISCVABI { 502 503 enum ABI { 504 ABI_ILP32, 505 ABI_ILP32F, 506 ABI_ILP32D, 507 ABI_ILP32E, 508 ABI_LP64, 509 ABI_LP64F, 510 ABI_LP64D, 511 ABI_LP64E, 512 ABI_Unknown 513 }; 514 515 // Returns the target ABI, or else a StringError if the requested ABIName is 516 // not supported for the given TT and FeatureBits combination. 517 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, 518 StringRef ABIName); 519 520 ABI getTargetABI(StringRef ABIName); 521 522 // Returns the register used to hold the stack pointer after realignment. 523 MCRegister getBPReg(); 524 525 // Returns the register holding shadow call stack pointer. 526 MCRegister getSCSPReg(); 527 528 } // namespace RISCVABI 529 530 namespace RISCVFeatures { 531 532 // Validates if the given combination of features are valid for the target 533 // triple. Exits with report_fatal_error if not. 534 void validate(const Triple &TT, const FeatureBitset &FeatureBits); 535 536 llvm::Expected<std::unique_ptr<RISCVISAInfo>> 537 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits); 538 539 } // namespace RISCVFeatures 540 541 namespace RISCVRVC { 542 bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI); 543 bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI); 544 } // namespace RISCVRVC 545 546 namespace RISCVZC { 547 enum RLISTENCODE { 548 RA = 4, 549 RA_S0, 550 RA_S0_S1, 551 RA_S0_S2, 552 RA_S0_S3, 553 RA_S0_S4, 554 RA_S0_S5, 555 RA_S0_S6, 556 RA_S0_S7, 557 RA_S0_S8, 558 RA_S0_S9, 559 // note - to include s10, s11 must also be included 560 RA_S0_S11, 561 INVALID_RLIST, 562 }; 563 564 inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) { 565 assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E"); 566 switch (EndReg) { 567 case RISCV::X1: 568 return RLISTENCODE::RA; 569 case RISCV::X8: 570 return RLISTENCODE::RA_S0; 571 case RISCV::X9: 572 return RLISTENCODE::RA_S0_S1; 573 case RISCV::X18: 574 return RLISTENCODE::RA_S0_S2; 575 case RISCV::X19: 576 return RLISTENCODE::RA_S0_S3; 577 case RISCV::X20: 578 return RLISTENCODE::RA_S0_S4; 579 case RISCV::X21: 580 return RLISTENCODE::RA_S0_S5; 581 case RISCV::X22: 582 return RLISTENCODE::RA_S0_S6; 583 case RISCV::X23: 584 return RLISTENCODE::RA_S0_S7; 585 case RISCV::X24: 586 return RLISTENCODE::RA_S0_S8; 587 case RISCV::X25: 588 return RLISTENCODE::RA_S0_S9; 589 case RISCV::X26: 590 return RLISTENCODE::INVALID_RLIST; 591 case RISCV::X27: 592 return RLISTENCODE::RA_S0_S11; 593 default: 594 llvm_unreachable("Undefined input."); 595 } 596 } 597 598 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) { 599 assert(RlistVal != RLISTENCODE::INVALID_RLIST && 600 "{ra, s0-s10} is not supported, s11 must be included."); 601 if (!IsRV64) { 602 switch (RlistVal) { 603 case RLISTENCODE::RA: 604 case RLISTENCODE::RA_S0: 605 case RLISTENCODE::RA_S0_S1: 606 case RLISTENCODE::RA_S0_S2: 607 return 16; 608 case RLISTENCODE::RA_S0_S3: 609 case RLISTENCODE::RA_S0_S4: 610 case RLISTENCODE::RA_S0_S5: 611 case RLISTENCODE::RA_S0_S6: 612 return 32; 613 case RLISTENCODE::RA_S0_S7: 614 case RLISTENCODE::RA_S0_S8: 615 case RLISTENCODE::RA_S0_S9: 616 return 48; 617 case RLISTENCODE::RA_S0_S11: 618 return 64; 619 } 620 } else { 621 switch (RlistVal) { 622 case RLISTENCODE::RA: 623 case RLISTENCODE::RA_S0: 624 return 16; 625 case RLISTENCODE::RA_S0_S1: 626 case RLISTENCODE::RA_S0_S2: 627 return 32; 628 case RLISTENCODE::RA_S0_S3: 629 case RLISTENCODE::RA_S0_S4: 630 return 48; 631 case RLISTENCODE::RA_S0_S5: 632 case RLISTENCODE::RA_S0_S6: 633 return 64; 634 case RLISTENCODE::RA_S0_S7: 635 case RLISTENCODE::RA_S0_S8: 636 return 80; 637 case RLISTENCODE::RA_S0_S9: 638 return 96; 639 case RLISTENCODE::RA_S0_S11: 640 return 112; 641 } 642 } 643 llvm_unreachable("Unexpected RlistVal"); 644 } 645 646 inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal, 647 int64_t StackAdjustment, bool IsRV64) { 648 if (RlistVal == RLISTENCODE::INVALID_RLIST) 649 return false; 650 unsigned StackAdjBase = getStackAdjBase(RlistVal, IsRV64); 651 StackAdjustment -= StackAdjBase; 652 if (StackAdjustment % 16 != 0) 653 return false; 654 SpimmVal = StackAdjustment / 16; 655 if (SpimmVal > 3) 656 return false; 657 return true; 658 } 659 660 void printRlist(unsigned SlistEncode, raw_ostream &OS); 661 } // namespace RISCVZC 662 663 } // namespace llvm 664 665 #endif 666