| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1389 SDValue &SOffset, SDValue &Offset, in SelectMUBUF()
1474 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFAddr64()
1521 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFScratchOffen()
1593 SDValue &SOffset, in SelectMUBUFScratchOffset()
1618 SDValue &SOffset, SDValue &Offset in SelectMUBUFOffset()
2370 SDValue SRsrc, VAddr, SOffset, Offset; in SelectATOMIC_CMP_SWAP() local
2388 SDValue SRsrc, SOffset, Offset; in SelectATOMIC_CMP_SWAP() local
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| H A D | AMDGPUInstructionSelector.cpp | 2387 Register VAddr, RSrcReg, SOffset; in selectG_AMDGPU_ATOMIC_CMPXCHG() local
2943 MachineOperand &SOffset = MI.getOperand(5); in selectAMDGPU_BUFFER_ATOMIC_FADD() local
4066 MachineIRBuilder &B, Register &SOffset, int64_t &ImmOffset) const { in splitIllegalMUBUFOffset()
4080 Register &SOffset, int64_t &Offset) const { in selectMUBUFAddr64Impl()
4130 MachineOperand &Root, Register &RSrcReg, Register &SOffset, in selectMUBUFOffsetImpl()
4158 Register SOffset; in selectMUBUFAddr64() local
4191 Register SOffset; in selectMUBUFOffset() local
4218 Register SOffset; in selectMUBUFAddr64Atomic() local
4251 Register SOffset; in selectMUBUFOffsetAtomic() local
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| H A D | SIRegisterInfo.cpp | 758 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex() local
1039 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
1829 auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset); in eliminateFrameIndex() local
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| H A D | AMDGPURegisterBankInfo.cpp | 1339 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1358 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1449 Register SOffset; in applyMappingSBufferLoad() local
1765 Register SOffset = MI.getOperand(4).getReg(); in selectStoreIntrinsic() local
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| H A D | AMDGPULegalizerInfo.cpp | 3691 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
3774 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
3975 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); in legalizeBufferAtomic() local
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| H A D | SILoadStoreOptimizer.cpp | 88 bool SOffset = false; member
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| H A D | GCNHazardRecognizer.cpp | 729 const MachineOperand *SOffset = in createsVALUHazard() local
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| H A D | SIInstrInfo.cpp | 329 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
5624 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
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| H A D | SIISelLowering.cpp | 6734 SDValue SOffset, in getBufferOffsetForMMO()
7868 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7880 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 729 unsigned SOffset = 0; in getMachineOpValue() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 292 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 1890 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4256 StackOffset &SOffset, in isAArch64FrameOffsetLegal()
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