1 /* $NetBSD: drm_scdc_helper.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #ifndef DRM_SCDC_HELPER_H
27 #define DRM_SCDC_HELPER_H
28
29 #include <linux/i2c.h>
30 #include <linux/types.h>
31
32 #define SCDC_SINK_VERSION 0x01
33
34 #define SCDC_SOURCE_VERSION 0x02
35
36 #define SCDC_UPDATE_0 0x10
37 #define SCDC_READ_REQUEST_TEST (1 << 2)
38 #define SCDC_CED_UPDATE (1 << 1)
39 #define SCDC_STATUS_UPDATE (1 << 0)
40
41 #define SCDC_UPDATE_1 0x11
42
43 #define SCDC_TMDS_CONFIG 0x20
44 #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
45 #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
46 #define SCDC_SCRAMBLING_ENABLE (1 << 0)
47
48 #define SCDC_SCRAMBLER_STATUS 0x21
49 #define SCDC_SCRAMBLING_STATUS (1 << 0)
50
51 #define SCDC_CONFIG_0 0x30
52 #define SCDC_READ_REQUEST_ENABLE (1 << 0)
53
54 #define SCDC_STATUS_FLAGS_0 0x40
55 #define SCDC_CH2_LOCK (1 << 3)
56 #define SCDC_CH1_LOCK (1 << 2)
57 #define SCDC_CH0_LOCK (1 << 1)
58 #define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
59 #define SCDC_CLOCK_DETECT (1 << 0)
60
61 #define SCDC_STATUS_FLAGS_1 0x41
62
63 #define SCDC_ERR_DET_0_L 0x50
64 #define SCDC_ERR_DET_0_H 0x51
65 #define SCDC_ERR_DET_1_L 0x52
66 #define SCDC_ERR_DET_1_H 0x53
67 #define SCDC_ERR_DET_2_L 0x54
68 #define SCDC_ERR_DET_2_H 0x55
69 #define SCDC_CHANNEL_VALID (1 << 7)
70
71 #define SCDC_ERR_DET_CHECKSUM 0x56
72
73 #define SCDC_TEST_CONFIG_0 0xc0
74 #define SCDC_TEST_READ_REQUEST (1 << 7)
75 #define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
76
77 #define SCDC_MANUFACTURER_IEEE_OUI 0xd0
78 #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
79
80 #define SCDC_DEVICE_ID 0xd3
81 #define SCDC_DEVICE_ID_SIZE 8
82
83 #define SCDC_DEVICE_HARDWARE_REVISION 0xdb
84 #define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
85 #define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
86
87 #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
88 #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
89
90 #define SCDC_MANUFACTURER_SPECIFIC 0xde
91 #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
92
93 ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
94 size_t size);
95 ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
96 const void *buffer, size_t size);
97
98 /**
99 * drm_scdc_readb - read a single byte from SCDC
100 * @adapter: I2C adapter
101 * @offset: offset of register to read
102 * @value: return location for the register value
103 *
104 * Reads a single byte from SCDC. This is a convenience wrapper around the
105 * drm_scdc_read() function.
106 *
107 * Returns:
108 * 0 on success or a negative error code on failure.
109 */
drm_scdc_readb(struct i2c_adapter * adapter,u8 offset,u8 * value)110 static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,
111 u8 *value)
112 {
113 return drm_scdc_read(adapter, offset, value, sizeof(*value));
114 }
115
116 /**
117 * drm_scdc_writeb - write a single byte to SCDC
118 * @adapter: I2C adapter
119 * @offset: offset of register to read
120 * @value: return location for the register value
121 *
122 * Writes a single byte to SCDC. This is a convenience wrapper around the
123 * drm_scdc_write() function.
124 *
125 * Returns:
126 * 0 on success or a negative error code on failure.
127 */
drm_scdc_writeb(struct i2c_adapter * adapter,u8 offset,u8 value)128 static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
129 u8 value)
130 {
131 return drm_scdc_write(adapter, offset, &value, sizeof(value));
132 }
133
134 bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);
135
136 bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
137 bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
138 #endif
139