1 /* $NetBSD: sa11x0_gpioreg.h,v 1.4 2009/05/29 14:06:53 rjs Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA (ichiro@ichiro.org). 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * SA-11x0 GPIO Register 33 */ 34 35 #define SAGPIO_NPORTS 8 36 37 /* GPIO pin-level register */ 38 #define SAGPIO_PLR 0x00 39 40 /* GPIO pin direction register */ 41 #define SAGPIO_PDR 0x04 42 43 /* GPIO pin output set register */ 44 #define SAGPIO_PSR 0x08 45 46 /* GPIO pin output clear register */ 47 #define SAGPIO_PCR 0x0C 48 49 /* GPIO rising-edge detect register */ 50 #define SAGPIO_RER 0x10 51 52 /* GPIO falling-edge detect register */ 53 #define SAGPIO_FER 0x14 54 55 /* GPIO edge-detect status register */ 56 #define SAGPIO_EDR 0x18 57 58 /* GPIO alternate function register */ 59 #define SAGPIO_AFR 0x1C 60 61 /* XXX */ 62 #define GPIO(x) (0x00000001 << (x)) 63 64 /* 65 * SA-11x0 GPIOs parameter 66 */ 67 /* 68 port name desc 69 0 Reserved 70 1 Reserved 71 2...9 LDD{8..15} LCD DATA(8-15) 72 10 SSP_TXD SSP transmit 73 11 SSP_RXD SSP receive 74 12 SSP_SCLK SSP serial clock 75 13 SSP_SFRM SSP frameclock 76 14 UART_TXD UART transmit 77 15 UART_RXD UART receive 78 16 GPCLK_OUT General-purpose clock out 79 17 Reserved 80 18 UART_SCLK Sample clock input 81 19 SSP_CLK Sample clock input 82 20 UART_SCLK3 Sample clock input 83 21 MCP_CLK MCP dock in 84 22 TREQA Either TIC request A 85 23 TREQB Either TIC request B 86 24 Reserved 87 25 RTC Real Time Clock 88 26 RCLK_OUT internal clock /2 89 27 32KHZ_OUT Raw 32.768kHz osc output 90 */ 91 92 #define GPIO_ALT_SSP_TXD (1 << 10) 93 #define GPIO_ALT_SSP_RXD (1 << 11) 94 #define GPIO_ALT_SSP_SCLK (1 << 12) 95 #define GPIO_ALT_SSP_SFRM (1 << 13) 96 #define GPIO_ALT_SSP_CLK (1 << 19) 97 98