Searched defs:RegWidth (Results 1 – 9 of 9) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 809 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias()
817 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias()
828 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias()
840 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias()
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| H A D | AArch64InstPrinter.cpp | 238 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
252 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
269 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1153 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { in usesRegister()
2184 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass()
2310 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth, in AddNextRegisterToList()
2435 unsigned RegWidth, in getRegularReg()
2513 unsigned &RegNum, unsigned &RegWidth, in ParseSpecialReg()
2528 unsigned &RegNum, unsigned &RegWidth, in ParseRegularReg()
2562 unsigned &RegWidth, in ParseRegList()
2616 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister()
2648 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister()
2685 unsigned RegWidth) { in updateGprCountSymbols()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 177 unsigned RegWidth = in getMemoryOpCost() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4796 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
4852 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
4916 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1044 const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8; in buildSpillLoadStore() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2855 unsigned RegWidth) { in SelectCVTFixedPosOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1489 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 6978 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst() local
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