1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the subtarget options of a Target machine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H 16 17 #include "llvm/CodeGen/PBQPRAConstraint.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/Support/CodeGen.h" 20 21 namespace llvm { 22 23 class DataLayout; 24 class MachineFunction; 25 class MachineInstr; 26 class SDep; 27 class SUnit; 28 class TargetFrameLowering; 29 class TargetInstrInfo; 30 class TargetLowering; 31 class TargetRegisterClass; 32 class TargetRegisterInfo; 33 class TargetSchedModel; 34 class TargetSelectionDAGInfo; 35 struct MachineSchedPolicy; 36 template <typename T> class SmallVectorImpl; 37 38 //===----------------------------------------------------------------------===// 39 /// 40 /// TargetSubtargetInfo - Generic base class for all target subtargets. All 41 /// Target-specific options that control code generation and printing should 42 /// be exposed through a TargetSubtargetInfo-derived class. 43 /// 44 class TargetSubtargetInfo : public MCSubtargetInfo { 45 TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 46 void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 47 protected: // Can only create subclasses... 48 TargetSubtargetInfo(); 49 public: 50 // AntiDepBreakMode - Type of anti-dependence breaking that should 51 // be performed before post-RA scheduling. 52 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 53 typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; 54 55 virtual ~TargetSubtargetInfo(); 56 57 // Interfaces to the major aspects of target machine information: 58 // 59 // -- Instruction opcode and operand information 60 // -- Pipelines and scheduling information 61 // -- Stack frame information 62 // -- Selection DAG lowering information 63 // 64 // N.B. These objects may change during compilation. It's not safe to cache 65 // them between functions. getInstrInfo()66 virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; } getFrameLowering()67 virtual const TargetFrameLowering *getFrameLowering() const { 68 return nullptr; 69 } getTargetLowering()70 virtual const TargetLowering *getTargetLowering() const { return nullptr; } getSelectionDAGInfo()71 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const { 72 return nullptr; 73 } getDataLayout()74 virtual const DataLayout *getDataLayout() const { return nullptr; } 75 76 /// getRegisterInfo - If register information is available, return it. If 77 /// not, return null. This is kept separate from RegInfo until RegInfo has 78 /// details of graph coloring register allocation removed from it. 79 /// getRegisterInfo()80 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; } 81 82 /// getInstrItineraryData - Returns instruction itinerary data for the target 83 /// or specific subtarget. 84 /// getInstrItineraryData()85 virtual const InstrItineraryData *getInstrItineraryData() const { 86 return nullptr; 87 } 88 89 /// Resolve a SchedClass at runtime, where SchedClass identifies an 90 /// MCSchedClassDesc with the isVariant property. This may return the ID of 91 /// another variant SchedClass, but repeated invocation must quickly terminate 92 /// in a nonvariant SchedClass. resolveSchedClass(unsigned SchedClass,const MachineInstr * MI,const TargetSchedModel * SchedModel)93 virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, 94 const TargetSchedModel* SchedModel) const { 95 return 0; 96 } 97 98 /// \brief Temporary API to test migration to MI scheduler. 99 bool useMachineScheduler() const; 100 101 /// \brief True if the subtarget should run MachineScheduler after aggressive 102 /// coalescing. 103 /// 104 /// This currently replaces the SelectionDAG scheduler with the "source" order 105 /// scheduler. It does not yet disable the postRA scheduler. 106 virtual bool enableMachineScheduler() const; 107 108 /// \brief True if the subtarget should run PostMachineScheduler. 109 /// 110 /// This only takes effect if the target has configured the 111 /// PostMachineScheduler pass to run, or if the global cl::opt flag, 112 /// MISchedPostRA, is set. 113 virtual bool enablePostMachineScheduler() const; 114 115 /// \brief True if the subtarget should run the atomic expansion pass. 116 virtual bool enableAtomicExpand() const; 117 118 /// \brief Override generic scheduling policy within a region. 119 /// 120 /// This is a convenient way for targets that don't provide any custom 121 /// scheduling heuristics (no custom MachineSchedStrategy) to make 122 /// changes to the generic scheduling policy. overrideSchedPolicy(MachineSchedPolicy & Policy,MachineInstr * begin,MachineInstr * end,unsigned NumRegionInstrs)123 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, 124 MachineInstr *begin, 125 MachineInstr *end, 126 unsigned NumRegionInstrs) const {} 127 128 // \brief Perform target specific adjustments to the latency of a schedule 129 // dependency. adjustSchedDependency(SUnit * def,SUnit * use,SDep & dep)130 virtual void adjustSchedDependency(SUnit *def, SUnit *use, 131 SDep& dep) const { } 132 133 // For use with PostRAScheduling: get the anti-dependence breaking that should 134 // be performed before post-RA scheduling. getAntiDepBreakMode()135 virtual AntiDepBreakMode getAntiDepBreakMode() const { 136 return ANTIDEP_NONE; 137 } 138 139 // For use with PostRAScheduling: in CriticalPathRCs, return any register 140 // classes that should only be considered for anti-dependence breaking if they 141 // are on the critical path. getCriticalPathRCs(RegClassVector & CriticalPathRCs)142 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 143 return CriticalPathRCs.clear(); 144 } 145 146 // For use with PostRAScheduling: get the minimum optimization level needed 147 // to enable post-RA scheduling. getOptLevelToEnablePostRAScheduler()148 virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const { 149 return CodeGenOpt::Default; 150 } 151 152 /// \brief True if the subtarget should run the local reassignment 153 /// heuristic of the register allocator. 154 /// This heuristic may be compile time intensive, \p OptLevel provides 155 /// a finer grain to tune the register allocator. 156 virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const; 157 158 /// \brief Enable use of alias analysis during code generation (during MI 159 /// scheduling, DAGCombine, etc.). 160 virtual bool useAA() const; 161 162 /// \brief Enable the use of the early if conversion pass. enableEarlyIfConversion()163 virtual bool enableEarlyIfConversion() const { return false; } 164 165 /// \brief Return PBQPConstraint(s) for the target. 166 /// 167 /// Override to provide custom PBQP constraints. getCustomPBQPConstraints()168 virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const { 169 return nullptr; 170 } 171 172 /// Enable tracking of subregister liveness in register allocator. enableSubRegLiveness()173 virtual bool enableSubRegLiveness() const { 174 return false; 175 } 176 }; 177 178 } // End llvm namespace 179 180 #endif 181