1 //===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the entry points for global functions defined in 10 // the LLVM NVPTX back-end. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H 15 #define LLVM_LIB_TARGET_NVPTX_NVPTX_H 16 17 #include "llvm/IR/PassManager.h" 18 #include "llvm/Pass.h" 19 #include "llvm/Support/AtomicOrdering.h" 20 #include "llvm/Support/CodeGen.h" 21 22 namespace llvm { 23 class FunctionPass; 24 class MachineFunctionPass; 25 class NVPTXTargetMachine; 26 class PassRegistry; 27 28 namespace NVPTXCC { 29 enum CondCodes { 30 EQ, 31 NE, 32 LT, 33 LE, 34 GT, 35 GE 36 }; 37 } 38 39 FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM, 40 llvm::CodeGenOptLevel OptLevel); 41 ModulePass *createNVPTXAssignValidGlobalNamesPass(); 42 ModulePass *createGenericToNVVMLegacyPass(); 43 ModulePass *createNVPTXCtorDtorLoweringLegacyPass(); 44 FunctionPass *createNVVMIntrRangePass(); 45 FunctionPass *createNVVMReflectPass(unsigned int SmVersion); 46 MachineFunctionPass *createNVPTXPrologEpilogPass(); 47 MachineFunctionPass *createNVPTXReplaceImageHandlesPass(); 48 FunctionPass *createNVPTXImageOptimizerPass(); 49 FunctionPass *createNVPTXLowerArgsPass(); 50 FunctionPass *createNVPTXLowerAllocaPass(); 51 FunctionPass *createNVPTXLowerUnreachablePass(bool TrapUnreachable, 52 bool NoTrapAfterNoreturn); 53 MachineFunctionPass *createNVPTXPeephole(); 54 MachineFunctionPass *createNVPTXProxyRegErasurePass(); 55 56 struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> { 57 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 58 }; 59 60 struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> { 61 NVVMReflectPass(); 62 NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {} 63 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 64 65 private: 66 unsigned SmVersion; 67 }; 68 69 struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> { 70 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 71 }; 72 73 struct NVPTXCopyByValArgsPass : PassInfoMixin<NVPTXCopyByValArgsPass> { 74 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 75 }; 76 77 namespace NVPTX { 78 enum DrvInterface { 79 NVCL, 80 CUDA 81 }; 82 83 // A field inside TSFlags needs a shift and a mask. The usage is 84 // always as follows : 85 // ((TSFlags & fieldMask) >> fieldShift) 86 // The enum keeps the mask, the shift, and all valid values of the 87 // field in one place. 88 enum VecInstType { 89 VecInstTypeShift = 0, 90 VecInstTypeMask = 0xF, 91 92 VecNOP = 0, 93 VecLoad = 1, 94 VecStore = 2, 95 VecBuild = 3, 96 VecShuffle = 4, 97 VecExtract = 5, 98 VecInsert = 6, 99 VecDest = 7, 100 VecOther = 15 101 }; 102 103 enum SimpleMove { 104 SimpleMoveMask = 0x10, 105 SimpleMoveShift = 4 106 }; 107 enum LoadStore { 108 isLoadMask = 0x20, 109 isLoadShift = 5, 110 isStoreMask = 0x40, 111 isStoreShift = 6 112 }; 113 114 // Extends LLVM AtomicOrdering with PTX Orderings: 115 using OrderingUnderlyingType = unsigned int; 116 enum Ordering : OrderingUnderlyingType { 117 NotAtomic = (OrderingUnderlyingType) 118 AtomicOrdering::NotAtomic, // PTX calls these: "Weak" 119 // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed 120 Relaxed = (OrderingUnderlyingType)AtomicOrdering::Monotonic, 121 // Consume = 3, // Unimplemented in LLVM; NVPTX would map to "Acquire" 122 Acquire = (OrderingUnderlyingType)AtomicOrdering::Acquire, 123 Release = (OrderingUnderlyingType)AtomicOrdering::Release, 124 AcquireRelease = (OrderingUnderlyingType)AtomicOrdering::AcquireRelease, 125 SequentiallyConsistent = 126 (OrderingUnderlyingType)AtomicOrdering::SequentiallyConsistent, 127 Volatile = SequentiallyConsistent + 1, 128 RelaxedMMIO = Volatile + 1, 129 LASTORDERING = RelaxedMMIO 130 }; 131 132 using ScopeUnderlyingType = unsigned int; 133 enum Scope : ScopeUnderlyingType { 134 Thread = 0, 135 Block = 1, 136 Cluster = 2, 137 Device = 3, 138 System = 4, 139 LASTSCOPE = System 140 }; 141 142 using AddressSpaceUnderlyingType = unsigned int; 143 enum AddressSpace : AddressSpaceUnderlyingType { 144 Generic = 0, 145 Global = 1, 146 Shared = 3, 147 Const = 4, 148 Local = 5, 149 150 // NVPTX Backend Private: 151 Param = 101 152 }; 153 154 namespace PTXLdStInstCode { 155 enum FromType { 156 Unsigned = 0, 157 Signed, 158 Float, 159 Untyped 160 }; 161 enum VecType { 162 Scalar = 1, 163 V2 = 2, 164 V4 = 4 165 }; 166 } // namespace PTXLdStInstCode 167 168 /// PTXCvtMode - Conversion code enumeration 169 namespace PTXCvtMode { 170 enum CvtMode { 171 NONE = 0, 172 RNI, 173 RZI, 174 RMI, 175 RPI, 176 RN, 177 RZ, 178 RM, 179 RP, 180 RNA, 181 182 BASE_MASK = 0x0F, 183 FTZ_FLAG = 0x10, 184 SAT_FLAG = 0x20, 185 RELU_FLAG = 0x40 186 }; 187 } 188 189 /// PTXCmpMode - Comparison mode enumeration 190 namespace PTXCmpMode { 191 enum CmpMode { 192 EQ = 0, 193 NE, 194 LT, 195 LE, 196 GT, 197 GE, 198 LO, 199 LS, 200 HI, 201 HS, 202 EQU, 203 NEU, 204 LTU, 205 LEU, 206 GTU, 207 GEU, 208 NUM, 209 // NAN is a MACRO 210 NotANumber, 211 212 BASE_MASK = 0xFF, 213 FTZ_FLAG = 0x100 214 }; 215 } 216 217 namespace PTXPrmtMode { 218 enum PrmtMode { 219 NONE, 220 F4E, 221 B4E, 222 RC8, 223 ECL, 224 ECR, 225 RC16, 226 }; 227 } 228 } 229 void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &); 230 } // namespace llvm 231 232 // Defines symbolic names for NVPTX registers. This defines a mapping from 233 // register name to register number. 234 #define GET_REGINFO_ENUM 235 #include "NVPTXGenRegisterInfo.inc" 236 237 // Defines symbolic names for the NVPTX instructions. 238 #define GET_INSTRINFO_ENUM 239 #define GET_INSTRINFO_MC_HELPER_DECLS 240 #include "NVPTXGenInstrInfo.inc" 241 242 #endif 243