Searched defs:Pg (Results 1 – 4 of 4) sorted by relevance
/netbsd-src/regress/sys/uvm/pdsim/ |
H A D | nbsd.hs | 40 data Page = Pg { pgid :: PageId, referenced :: Bool } constructor
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 371 IntrinsicInst *Pg = dyn_cast<IntrinsicInst>(II.getArgOperand(1)); in instCombineSVEDup() local 395 Value *Pg = II.getArgOperand(0); in instCombineSVELast() local
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H A D | AArch64ISelLowering.cpp | 13788 static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, in getPTest() 13901 SDValue Pg = N->getOperand(1); in convertMergedOpToPredOp() local 14617 SDValue Pg = N->getOperand(1); in performGLD1Combine() local 17391 auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT); in convertFixedMaskToScalableVector() local 17650 auto Pg = getPredicateForVector(DAG, DL, VT); in LowerToPredicatedOp() local 17743 SDValue Pg = getPredicateForVector(DAG, DL, SrcVT); in LowerVECREDUCE_SEQ_FADD() local 17767 SDValue Pg = getPredicateForVector(DAG, DL, OpVT); in LowerPredReductionToSVE() local 17809 SDValue Pg = getPredicateForVector(DAG, DL, SrcVT); in LowerReductionToSVE() local 17859 auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT); in LowerFixedLengthVectorSetccToSVE() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 143 unsigned Pg; member in __anon65f0dadd0111::AArch64AsmParser::PrefixInfo
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