| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 358 bool isSALU(uint16_t Opcode) const { in isSALU()
366 bool isVALU(uint16_t Opcode) const { in isVALU()
374 bool isVMEM(uint16_t Opcode) const { in isVMEM()
382 bool isSOP1(uint16_t Opcode) const { in isSOP1()
390 bool isSOP2(uint16_t Opcode) const { in isSOP2()
398 bool isSOPC(uint16_t Opcode) const { in isSOPC()
406 bool isSOPK(uint16_t Opcode) const { in isSOPK()
414 bool isSOPP(uint16_t Opcode) const { in isSOPP()
422 bool isPacked(uint16_t Opcode) const { in isPacked()
430 bool isVOP1(uint16_t Opcode) const { in isVOP1()
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVMakeCompressible.cpp | 100 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth()
119 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in compressedLDSTOffsetMask()
125 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in compressibleSPOffset()
133 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) { in getBaseAdjustForCompression()
148 const unsigned Opcode = MI.getOpcode(); in isCompressibleLoad() local
157 const unsigned Opcode = MI.getOpcode(); in isCompressibleStore() local
176 const unsigned Opcode = MI.getOpcode(); in getRegImmPairPreventingCompression() local
289 unsigned Opcode = MI.getOpcode(); in updateOperands() local
368 unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg) in runOnMachineFunction() local
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| H A D | RISCVTargetTransformInfo.cpp | 98 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst()
330 RISCVTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, in getMaskedMemoryOpCost()
342 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost()
913 InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, in getCastInstrCost()
1024 RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, in getArithmeticReductionCost()
1055 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, in getExtendedReductionCost()
1104 InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
1117 InstructionCost RISCVTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
1200 InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
1296 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
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| /openbsd-src/gnu/llvm/lldb/source/Plugins/Instruction/PPC64/ |
| H A D | EmulateInstructionPPC64.h | 71 struct Opcode { struct
80 Opcode *GetOpcodeForInstruction(uint32_t opcode); argument
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| /openbsd-src/gnu/llvm/lldb/source/Plugins/Instruction/LoongArch/ |
| H A D | EmulateInstructionLoongArch.h | 66 struct Opcode { struct
74 Opcode *GetOpcodeForInstruction(uint32_t inst); argument
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| /openbsd-src/gnu/llvm/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
134 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
139 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
146 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
153 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
169 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
196 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZShortenInst.cpp | 110 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
120 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
132 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
145 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
158 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
180 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) { in shortenFusedFPOp()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 146 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
160 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
170 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
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| H A D | LanaiRegisterInfo.cpp | 69 static bool isALUArithLoOpcode(unsigned Opcode) { in isALUArithLoOpcode()
85 static unsigned getOppositeALULoOpcode(unsigned Opcode) { in getOppositeALULoOpcode()
108 static unsigned getRRMOpcodeVariant(unsigned Opcode) { in getRRMOpcodeVariant()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes()
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| /openbsd-src/gnu/llvm/lldb/include/lldb/Core/ |
| H A D | Opcode.h | 43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.h | 84 unsigned Opcode; member
179 void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeScalarToDifferentSizeStrategy()
190 void setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeVectorElementToDifferentSizeStrategy()
320 void setScalarAction(const unsigned Opcode, const unsigned TypeIndex, in setScalarAction()
326 void setPointerAction(const unsigned Opcode, const unsigned TypeIndex, in setPointerAction()
343 void setScalarInVectorAction(const unsigned Opcode, const unsigned TypeIndex, in setScalarInVectorAction()
354 void setVectorNumElementAction(const unsigned Opcode, in setVectorNumElementAction()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 96 bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) { in isLoadInst()
118 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local
156 unsigned Opcode) { in checkShift()
186 unsigned Opcode = I->getParent()->getOpcode(); in processCandidate() local
242 unsigned Opcode = Inst->getOpcode(); in processInst() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCPredicates.cpp | 18 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
52 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 232 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst()
555 InstructionCost PPCTTIImpl::vectorCostAdjustmentFactor(unsigned Opcode, in vectorCostAdjustmentFactor()
587 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
630 InstructionCost PPCTTIImpl::getCFInstrCost(unsigned Opcode, in getCFInstrCost()
639 InstructionCost PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, in getCastInstrCost()
659 InstructionCost PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
677 InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
751 InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
840 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost()
999 bool PPCTTIImpl::hasActiveVectorLength(unsigned Opcode, Type *DataType, in hasActiveVectorLength()
[all …]
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| H A D | PPCInstrInfo.h | 313 bool isXFormMemOp(unsigned Opcode) const { in isXFormMemOp()
316 bool isPrefixed(unsigned Opcode) const { in isPrefixed()
319 bool isSExt32To64(unsigned Opcode) const { in isSExt32To64()
322 bool isZExt32To64(unsigned Opcode) const { in isZExt32To64()
328 bool isNoTOCCallInstr(unsigned Opcode) const { in isNoTOCCallInstr()
419 static bool isSameClassPhysRegCopy(unsigned Opcode) { in isSameClassPhysRegCopy()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 178 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
236 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost()
252 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost()
259 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost()
271 InstructionCost HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
287 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
307 InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, in getCastInstrCost()
334 InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 106 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; in IfNeededExtSP() local
128 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in IfNeededLDAWSP() local
201 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in RestoreSpillList() local
262 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; in emitPrologue() local
287 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in emitPrologue() local
400 int Opcode = isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6; in emitEpilogue() local
407 int Opcode = isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 : in emitEpilogue() local
512 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; in eliminateCallFramePseudoInstr() local
516 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in eliminateCallFramePseudoInstr() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | LeonPasses.cpp | 48 unsigned Opcode = MI.getOpcode(); in runOnMachineFunction() local
81 unsigned Opcode = MI.getOpcode(); in runOnMachineFunction() local
132 unsigned Opcode = MI.getOpcode(); in runOnMachineFunction() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 500 bool isFpMLxInstruction(unsigned Opcode) const { in isFpMLxInstruction()
514 bool canCauseFpMLxStall(unsigned Opcode) const { in canCauseFpMLxStall()
587 unsigned VCMPOpcodeToVPT(unsigned Opcode) { in VCMPOpcodeToVPT()
896 inline bool isLegalAddressImm(unsigned Opcode, int Imm, in isLegalAddressImm()
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| H A D | ARMTargetTransformInfo.cpp | 330 InstructionCost ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, in getIntImmCodeSizeCost()
387 InstructionCost ARMTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst()
458 InstructionCost ARMTTIImpl::getCFInstrCost(unsigned Opcode, in getCFInstrCost()
472 InstructionCost ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, in getCastInstrCost()
876 InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, in getVectorInstrCost()
915 InstructionCost ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
1317 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
1457 InstructionCost ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
1505 ARMTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, in getMaskedMemoryOpCost()
1523 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost()
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AVR/ |
| H A D | AVRFrameLowering.cpp | 124 unsigned Opcode = (isUInt<6>(FrameSize) && STI.hasADDSUBIW()) ? AVR::SBIWRdK in emitPrologue() local
203 unsigned Opcode; in emitEpilogue() local
320 unsigned Opcode = MI.getOpcode(); in fixStackStores() local
350 unsigned int Opcode = MI->getOpcode(); in eliminateCallFramePseudoInstr() local
458 int Opcode = MI.getOpcode(); in runOnMachineFunction() local
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| /openbsd-src/gnu/llvm/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 63 const MCInstrDesc &get(unsigned Opcode) const { in get()
70 StringRef getName(unsigned Opcode) const { in getName()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 53 unsigned Opcode = Mips::Mflo16; in selectMULT() local
58 unsigned Opcode = Mips::Mfhi16; in selectMULT() local
180 unsigned Opcode = Node->getOpcode(); in trySelect() local
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