1 /* $NetBSD: if_scx.c,v 1.44 2024/06/29 11:27:12 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2020 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Tohru Nishimura.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #define NOT_MP_SAFE 0
33
34 /*
35 * Socionext SC2A11 SynQuacer NetSec GbE driver
36 *
37 * Multiple Tx and Rx queues exist inside and dedicated descriptor
38 * fields specifies which queue is to use. Three internal micro-processors
39 * to handle incoming frames, outgoing frames and packet data crypto
40 * processing. uP programs are stored in an external flash memory and
41 * have to be loaded by device driver.
42 * NetSec uses Synopsys DesignWare Core EMAC. DWC implementation
43 * register (0x20) is known to have 0x10.36 and feature register (0x1058)
44 * reports 0x11056f37.
45 * <24> alternative/enhanced desc format
46 * <18> receive IP type 2 checksum offload
47 * <16> transmit checksum offload
48 * <11> event counter (mac management counter, MMC)
49 */
50
51 #include <sys/cdefs.h>
52 __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.44 2024/06/29 11:27:12 riastradh Exp $");
53
54 #include <sys/param.h>
55 #include <sys/bus.h>
56 #include <sys/intr.h>
57 #include <sys/device.h>
58 #include <sys/callout.h>
59 #include <sys/mbuf.h>
60 #include <sys/errno.h>
61 #include <sys/rndsource.h>
62 #include <sys/kernel.h>
63 #include <sys/systm.h>
64
65 #include <net/if.h>
66 #include <net/if_media.h>
67 #include <net/if_dl.h>
68 #include <net/if_ether.h>
69 #include <dev/mii/mii.h>
70 #include <dev/mii/miivar.h>
71 #include <net/bpf.h>
72
73 #include <dev/fdt/fdtvar.h>
74 #include <dev/acpi/acpireg.h>
75 #include <dev/acpi/acpivar.h>
76 #include <dev/acpi/acpi_intr.h>
77
78 /* SC2A11 GbE has 64-bit paddr descriptor */
79 struct tdes {
80 uint32_t t0, t1, t2, t3;
81 };
82 struct rdes {
83 uint32_t r0, r1, r2, r3;
84 };
85 #define T0_OWN (1U<<31) /* desc is ready to Tx */
86 #define T0_LD (1U<<30) /* last descriptor in array */
87 #define T0_DRID (24) /* 29:24 desc ring id */
88 #define T0_PT (1U<<21) /* 23:21 "pass-through" */
89 #define T0_TDRID (16) /* 20:16 target desc ring id: GMAC=15 */
90 #define T0_CC (1U<<15) /* ??? */
91 #define T0_FS (1U<<9) /* first segment of frame */
92 #define T0_LS (1U<<8) /* last segment of frame */
93 #define T0_CSUM (1U<<7) /* enable check sum offload */
94 #define T0_TSO (1U<<6) /* enable TCP segment offload */
95 #define T0_TRS (1U<<4) /* 5:4 "TRS" ??? */
96 /* T1 frame segment address 63:32 */
97 /* T2 frame segment address 31:0 */
98 /* T3 31:16 TCP segment length, 15:0 frame segment length to transmit */
99 #define R0_OWN (1U<<31) /* desc is empty */
100 #define R0_LD (1U<<30) /* last descriptor in array */
101 #define R0_SDRID (24) /* 29:24 source desc ring id */
102 #define R0_FR (1U<<23) /* found fragmented */
103 #define R0_ER (1U<<21) /* Rx error indication */
104 #define R0_ERR (3U<<16) /* 18:16 receive error code */
105 #define R0_TDRID (12) /* 15:12 target desc ring id */
106 #define R0_FS (1U<<9) /* first segment of frame */
107 #define R0_LS (1U<<8) /* last segment of frame */
108 #define R0_CSUM (3U<<6) /* 7:6 checksum status, 0: undone */
109 #define R0_CERR (2U<<6) /* 2: found bad */
110 #define R0_COK (1U<<6) /* 1: found ok */
111 /* R1 frame address 63:32 */
112 /* R2 frame address 31:0 */
113 /* R3 31:16 received frame length, 15:0 buffer length to receive */
114
115 /*
116 * SC2A11 registers. 0x100 - 1204
117 */
118 #define SWRESET 0x104
119 #define SRST_RUN (1U<<31) /* instruct start, 0 to stop */
120 #define COMINIT 0x120
121 #define INIT_DB (1U<<2) /* ???; self clear when done */
122 #define INIT_CLS (1U<<1) /* ???; self clear when done */
123 #define xINTSR 0x200 /* aggregated interrupt status */
124 #define IRQ_UCODE (1U<<20) /* ucode load completed; W1C */
125 #define IRQ_MAC (1U<<19) /* ??? */
126 #define IRQ_PKT (1U<<18) /* ??? */
127 #define IRQ_BOOTCODE (1U<<5) /* ??? */
128 #define IRQ_XDONE (1U<<4) /* ??? mode change completed */
129 #define IRQ_RX (1U<<1) /* top level Rx interrupt */
130 #define IRQ_TX (1U<<0) /* top level Tx interrupt */
131 #define xINTAEN 0x204 /* INT_A enable */
132 #define xINTAE_SET 0x234 /* bit to set */
133 #define xINTAE_CLR 0x238 /* bit to clr */
134 #define xINTBEN 0x23c /* INT_B enable */
135 #define xINTBE_SET 0x240 /* bit to set */
136 #define xINTBE_CLR 0x244 /* bit to clr */
137 #define TXISR 0x400 /* transmit status; W1C */
138 #define TXIEN 0x404 /* tx interrupt enable */
139 #define TXIE_SET 0x428 /* bit to set */
140 #define TXIE_CLR 0x42c /* bit to clr */
141 #define TXI_NTOWNR (1U<<17) /* ??? desc array got empty */
142 #define TXI_TR_ERR (1U<<16) /* xmit error detected */
143 #define TXI_TXDONE (1U<<15) /* xmit completed */
144 #define TXI_TMREXP (1U<<14) /* coalesce guard timer expired */
145 #define RXISR 0x440 /* receive status; W1C */
146 #define RXIEN 0x444 /* rx interrupt enable */
147 #define RXIE_SET 0x468 /* bit to set */
148 #define RXIE_CLR 0x46c /* bit to clr */
149 #define RXI_RC_ERR (1U<<16) /* recv error detected */
150 #define RXI_PKTCNT (1U<<15) /* recv counter has new value */
151 #define RXI_TMREXP (1U<<14) /* coalesce guard timer expired */
152 #define TDBA_LO 0x408 /* tdes array base addr 31:0 */
153 #define TDBA_HI 0x434 /* tdes array base addr 63:32 */
154 #define RDBA_LO 0x448 /* rdes array base addr 31:0 */
155 #define RDBA_HI 0x474 /* rdes array base addr 63:32 */
156 #define TXCONF 0x430 /* tdes config */
157 #define RXCONF 0x470 /* rdes config */
158 #define DESCNF_UP (1U<<31) /* 'up-and-running' */
159 #define DESCNF_CHRST (1U<<30) /* channel reset */
160 #define DESCNF_TMR (1U<<4) /* coalesce timer unit select */
161 #define DESCNF_LE (1) /* little endian desc format */
162 #define TXSUBMIT 0x410 /* submit frame(s) to transmit */
163 #define TXCOALESC 0x418 /* tx intr coalesce upper bound */
164 #define RXCOALESC 0x458 /* rx intr coalesce upper bound */
165 #define TCLSCTIME 0x420 /* tintr guard time usec */
166 #define RCLSCTIME 0x460 /* rintr guard time usec */
167 #define TXDONECNT 0x414 /* tx completed count, auto-zero */
168 #define RXAVAILCNT 0x454 /* rx available count, auto-zero */
169 #define DMACTL_TMR 0x20c /* DMA cycle tick value */
170 #define PKTCTRL 0x140 /* pkt engine control */
171 #define MODENRM (1U<<28) /* set operational mode to 'normal' */
172 #define ENJUMBO (1U<<27) /* allow jumbo frame */
173 #define RPTCSUMERR (1U<<3) /* log Rx checksum error */
174 #define RPTHDCOMP (1U<<2) /* log header incomplete condition */
175 #define RPTHDERR (1U<<1) /* log header error */
176 #define DROPNOMATCH (1U<<0) /* drop no match frames */
177 #define UCODE_PKT 0x0d0 /* packet engine ucode port */
178 #define UCODE_H2M 0x210 /* host2media engine ucode port */
179 #define UCODE_M2H 0x21c /* media2host engine ucode port */
180 #define CORESTAT 0x218 /* engine run state */
181 #define PKTSTOP (1U<<2) /* pkt engine stopped */
182 #define M2HSTOP (1U<<1) /* M2H engine stopped */
183 #define H2MSTOP (1U<<0) /* H2M engine stopped */
184 #define DMACTL_H2M 0x214 /* host2media engine control */
185 #define DMACTL_M2H 0x220 /* media2host engine control */
186 #define DMACTL_STOP (1U<<0) /* instruct stop; self-clear */
187 #define M2H_MODE_TRANS (1U<<20) /* initiate M2H mode change */
188 #define MODE_TRANS 0x500 /* mode change completion status */
189 #define N2T_DONE (1U<<20) /* normal->taiki change completed */
190 #define T2N_DONE (1U<<19) /* taiki->normal change completed */
191 #define CLKEN 0x100 /* clock distribution enable */
192 #define CLK_G (1U<<5) /* feed clk domain G */
193 #define CLK_C (1U<<1) /* feed clk domain C */
194 #define CLK_D (1U<<0) /* feed clk domain D */
195 #define DESC_INIT 0x11fc /* write 1 for desc init, SC */
196 #define DESC_SRST 0x1204 /* write 1 for desc sw reset, SC */
197
198 /* GMAC register indirect access. thru MACCMD/MACDATA operation */
199 #define MACDATA 0x11c0 /* gmac register rd/wr data */
200 #define MACCMD 0x11c4 /* gmac register operation */
201 #define CMD_IOWR (1U<<28) /* write op */
202 #define CMD_BUSY (1U<<31) /* busy bit */
203 #define MACSTAT 0x1024 /* mac interrupt status (unused) */
204 #define MACINTE 0x1028 /* mac interrupt enable (unused) */
205
206 #define FLOWTHR 0x11cc /* flow control threshold */
207 /* 31:16 pause threshold, 15:0 resume threshold */
208 #define INTF_SEL 0x11d4 /* phy interface type */
209 #define INTF_GMII 0
210 #define INTF_RGMII 1
211 #define INTF_RMII 4
212
213 #define MCVER 0x22c /* micro controller version */
214 #define HWVER 0x230 /* hardware version */
215
216 /*
217 * GMAC registers are mostly identical to Synopsys DesignWare Core
218 * Ethernet. These must be handled by indirect access.
219 */
220 #define GMACMCR 0x0000 /* MAC configuration */
221 #define MCR_IBN (1U<<30) /* watch in-band-signal */
222 #define MCR_CST (1U<<25) /* strip CRC */
223 #define MCR_TC (1U<<24) /* keep RGMII PHY notified */
224 #define MCR_WD (1U<<23) /* allow long >2048 tx frame */
225 #define MCR_JE (1U<<20) /* allow ~9018 tx jumbo frame */
226 #define MCR_IFG (7U<<17) /* 19:17 IFG value 0~7 */
227 #define MCR_DCRS (1U<<16) /* ignore (G)MII HDX Tx error */
228 #define MCR_PS (1U<<15) /* 1: MII 10/100, 0: GMII 1000 */
229 #define MCR_FES (1U<<14) /* force speed 100 */
230 #define MCR_DO (1U<<13) /* don't receive my own HDX Tx frames */
231 #define MCR_LOOP (1U<<12) /* run loop back */
232 #define MCR_USEFDX (1U<<11) /* force full duplex */
233 #define MCR_IPCEN (1U<<10) /* handle checksum */
234 #define MCR_DR (1U<<9) /* attempt no tx retry, send once */
235 #define MCR_LUD (1U<<8) /* link condition report when RGMII */
236 #define MCR_ACS (1U<<7) /* auto pad auto strip CRC */
237 #define MCR_DC (1U<<4) /* report excessive tx deferral */
238 #define MCR_TE (1U<<3) /* run Tx MAC engine, 0 to stop */
239 #define MCR_RE (1U<<2) /* run Rx MAC engine, 0 to stop */
240 #define MCR_PREA (3U) /* 1:0 preamble len. 0~2 */
241 #define GMACAFR 0x0004 /* frame DA/SA address filter */
242 #define AFR_RA (1U<<31) /* accept all irrespective of filt. */
243 #define AFR_HPF (1U<<10) /* hash+perfect filter, or hash only */
244 #define AFR_SAF (1U<<9) /* source address filter */
245 #define AFR_SAIF (1U<<8) /* SA inverse filtering */
246 #define AFR_PCF (2U<<6) /* 7:6 accept pause frame 0~3 */
247 #define AFR_DBF (1U<<5) /* reject broadcast frame */
248 #define AFR_PM (1U<<4) /* accept all multicast frame */
249 #define AFR_DAIF (1U<<3) /* DA inverse filtering */
250 #define AFR_MHTE (1U<<2) /* use multicast hash table */
251 #define AFR_UHTE (1U<<1) /* use hash table for unicast */
252 #define AFR_PR (1U<<0) /* run promisc mode */
253 #define GMACGAR 0x0010 /* MDIO operation */
254 #define GAR_PHY (11) /* 15:11 mii phy */
255 #define GAR_REG (6) /* 10:6 mii reg */
256 #define GAR_CLK (2) /* 5:2 mdio clock tick ratio */
257 #define GAR_IOWR (1U<<1) /* MDIO write op */
258 #define GAR_BUSY (1U<<0) /* busy bit */
259 #define GAR_MDIO_25_35MHZ 2
260 #define GAR_MDIO_35_60MHZ 3
261 #define GAR_MDIO_60_100MHZ 0
262 #define GAR_MDIO_100_150MHZ 1
263 #define GAR_MDIO_150_250MHZ 4
264 #define GAR_MDIO_250_300MHZ 5
265 #define GMACGDR 0x0014 /* MDIO rd/wr data */
266 #define GMACFCR 0x0018 /* 802.3x flowcontrol */
267 /* 31:16 pause timer value, 5:4 pause timer threshold */
268 #define FCR_RFE (1U<<2) /* accept PAUSE to throttle Tx */
269 #define FCR_TFE (1U<<1) /* generate PAUSE to moderate Rx lvl */
270 #define GMACIMPL 0x0020 /* implementation id */
271 #define GMACISR 0x0038 /* interrupt status indication */
272 #define GMACIMR 0x003c /* interrupt mask to inhibit */
273 #define ISR_TS (1U<<9) /* time stamp operation detected */
274 #define ISR_CO (1U<<7) /* Rx checksum offload completed */
275 #define ISR_TX (1U<<6) /* Tx completed */
276 #define ISR_RX (1U<<5) /* Rx completed */
277 #define ISR_ANY (1U<<4) /* any of above 5-7 report */
278 #define ISR_LC (1U<<0) /* link status change detected */
279 #define GMACMAH0 0x0040 /* my own MAC address 47:32 */
280 #define GMACMAL0 0x0044 /* my own MAC address 31:0 */
281 #define GMACMAH(i) ((i)*8+0x40) /* supplemental MAC addr 1-15 */
282 #define GMACMAL(i) ((i)*8+0x44) /* 31:0 MAC address low part */
283 /* MAH bit-31: slot in use, 30: SA to match, 29:24 byte-wise don'care */
284 #define GMACAMAH(i) ((i)*8+0x800) /* supplemental MAC addr 16-31 */
285 #define GMACAMAL(i) ((i)*8+0x804) /* 31: MAC address low part */
286 /* supplimental MAH bit-31: slot in use, no other bit is effective */
287 #define GMACMHTH 0x0008 /* 64bit multicast hash table 63:32 */
288 #define GMACMHTL 0x000c /* 64bit multicast hash table 31:0 */
289 #define GMACMHT(i) ((i)*4+0x500) /* 256-bit alternative mcast hash 0-7 */
290 #define GMACVTAG 0x001c /* VLAN tag control */
291 #define VTAG_HASH (1U<<19) /* use VLAN tag hash table */
292 #define VTAG_SVLAN (1U<<18) /* handle type 0x88A8 SVLAN frame */
293 #define VTAG_INV (1U<<17) /* run inverse match logic */
294 #define VTAG_ETV (1U<<16) /* use only 12bit VID field to match */
295 /* 15:0 concat of PRIO+CFI+VID */
296 #define GMACVHT 0x0588 /* 16-bit VLAN tag hash */
297 #define GMACMIISR 0x00d8 /* resolved RGMII/SGMII link status */
298 #define MIISR_LUP (1U<<3) /* link up(1)/down(0) report */
299 #define MIISR_SPD (3U<<1) /* 2:1 speed 10(0)/100(1)/1000(2) */
300 #define MIISR_FDX (1U<<0) /* fdx detected */
301
302 #define GMACLPIS 0x0030 /* LPI control & status */
303 #define LPIS_TXA (1U<<19) /* complete Tx in progress and LPI */
304 #define LPIS_PLS (1U<<17)
305 #define LPIS_EN (1U<<16) /* 1: enter LPI mode, 0: exit */
306 #define LPIS_TEN (1U<<0) /* Tx LPI report */
307 #define GMACLPIC 0x0034 /* LPI timer control */
308 #define LPIC_LST (5) /* 16:5 ??? */
309 #define LPIC_TWT (0) /* 15:0 ??? */
310 /* 0x700-764 Time Stamp control */
311
312 #define GMACBMR 0x1000 /* DMA bus mode control */
313 /* 24 8xPBL multiply by 8 for RPBL & PBL values
314 * 23 USP 1 to use RPBL for Rx DMA burst, 0 to share PBL by Rx and Tx
315 * 22:17 RPBL
316 * 16 FB fixed burst
317 * 15:14 priority between Rx and Tx
318 * 3 rxtx ratio 41
319 * 2 rxtx ratio 31
320 * 1 rxtx ratio 21
321 * 0 rxtx ratio 11
322 * 13:8 PBL possible DMA burst length
323 * 7 ATDS select 32-byte descriptor format for advanced features
324 * 6:2 DSL descriptor skip length, 0 for adjuscent, counted on bus width
325 * 0 MAC reset op. self-clear
326 */
327 #define BMR_RST (1) /* reset op. self clear when done */
328 #define GMACTPD 0x1004 /* write any to resume tdes */
329 #define GMACRPD 0x1008 /* write any to resume rdes */
330 #define GMACRDLA 0x100c /* rdes base address 32bit paddr */
331 #define GMACTDLA 0x1010 /* tdes base address 32bit paddr */
332 #define GMACDSR 0x1014 /* DMA status detail report; W1C */
333 #define GMACDIE 0x101c /* DMA interrupt enable */
334 #define DMAI_LPI (1U<<30) /* LPI interrupt */
335 #define DMAI_TTI (1U<<29) /* timestamp trigger interrupt */
336 #define DMAI_GMI (1U<<27) /* management counter interrupt */
337 #define DMAI_GLI (1U<<26) /* xMII link change detected */
338 #define DMAI_EB (23) /* 25:23 DMA bus error detected */
339 #define DMAI_TS (20) /* 22:20 Tx DMA state report */
340 #define DMAI_RS (17) /* 29:17 Rx DMA state report */
341 #define DMAI_NIS (1U<<16) /* normal interrupt summary; W1C */
342 #define DMAI_AIS (1U<<15) /* abnormal interrupt summary; W1C */
343 #define DMAI_ERI (1U<<14) /* the first Rx buffer is filled */
344 #define DMAI_FBI (1U<<13) /* DMA bus error detected */
345 #define DMAI_ETI (1U<<10) /* single frame Tx completed */
346 #define DMAI_RWT (1U<<9) /* longer than 2048 frame received */
347 #define DMAI_RPS (1U<<8) /* Rx process is now stopped */
348 #define DMAI_RU (1U<<7) /* Rx descriptor not available */
349 #define DMAI_RI (1U<<6) /* frame Rx completed by !R1_DIC */
350 #define DMAI_UNF (1U<<5) /* Tx underflow detected */
351 #define DMAI_OVF (1U<<4) /* receive buffer overflow detected */
352 #define DMAI_TJT (1U<<3) /* longer than 2048 frame sent */
353 #define DMAI_TU (1U<<2) /* Tx descriptor not available */
354 #define DMAI_TPS (1U<<1) /* transmission is stopped */
355 #define DMAI_TI (1U<<0) /* frame Tx completed by T0_IC */
356 #define GMACOMR 0x1018 /* DMA operation mode */
357 #define OMR_DT (1U<<26) /* don't drop error frames */
358 #define OMR_RSF (1U<<25) /* 1: Rx store&forward, 0: immed. */
359 #define OMR_DFF (1U<<24) /* don't flush rx frames on shortage */
360 #define OMR_TSF (1U<<21) /* 1: Tx store&forward, 0: immed. */
361 #define OMR_FTF (1U<<20) /* initiate tx FIFO reset, SC */
362 #define OMR_TTC (14) /* 16:14 Tx threshold */
363 #define OMR_ST (1U<<13) /* run Tx DMA engine, 0 to stop */
364 #define OMR_RFD (11) /* 12:11 Rx FIFO fill level */
365 #define OMR_EFC (1U<<8) /* transmit PAUSE to throttle Rx lvl. */
366 #define OMR_FEF (1U<<7) /* allow to receive error frames */
367 #define OMR_SR (1U<<1) /* run Rx DMA engine, 0 to stop */
368 #define GMACEVCS 0x1020 /* missed frame or ovf detected */
369 #define GMACRWDT 0x1024 /* enable rx watchdog timer interrupt */
370 #define GMACAXIB 0x1028 /* AXI bus mode control */
371 #define GMACAXIS 0x102c /* AXI status report */
372 /* 0x1048 current tx desc address */
373 /* 0x104c current rx desc address */
374 /* 0x1050 current tx buffer address */
375 /* 0x1054 current rx buffer address */
376 #define HWFEA 0x1058 /* DWC feature report */
377 #define FEA_EXDESC (1U<<24) /* alternative/enhanced desc layout */
378 #define FEA_2COE (1U<<18) /* Rx type 2 IP checksum offload */
379 #define FEA_1COE (1U<<17) /* Rx type 1 IP checksum offload */
380 #define FEA_TXOE (1U<<16) /* Tx checksum offload */
381 #define FEA_MMC (1U<<11) /* RMON event counter */
382
383 #define GMACEVCTL 0x0100 /* event counter control */
384 #define EVC_FHP (1U<<5) /* full-half preset */
385 #define EVC_CP (1U<<4) /* counter preset */
386 #define EVC_MCF (1U<<3) /* counter freeze */
387 #define EVC_ROR (1U<<2) /* auto-zero on counter read */
388 #define EVC_CSR (1U<<1) /* counter stop rollover */
389 #define EVC_CR (1U<<0) /* reset counters */
390 #define GMACEVCNT(i) ((i)*4+0x114) /* 80 event counters 0x114 - 0x284 */
391
392 /* 0x400-4ac L3/L4 control */
393
394 /*
395 * flash memory layout
396 * 0x00 - 07 48-bit MAC station address. 4 byte wise in BE order.
397 * 0x08 - 0b H->MAC xfer engine program start addr 63:32.
398 * 0x0c - 0f H2M program addr 31:0 (these are absolute addr, not offset)
399 * 0x10 - 13 H2M program length in 4 byte count.
400 * 0x14 - 0b M->HOST xfer engine program start addr 63:32.
401 * 0x18 - 0f M2H program addr 31:0 (absolute addr, not relative)
402 * 0x1c - 13 M2H program length in 4 byte count.
403 * 0x20 - 23 packet engine program addr 31:0, (absolute addr, not offset)
404 * 0x24 - 27 packet program length in 4 byte count.
405 *
406 * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0.
407 */
408
409 #define _BMR 0x00412080 /* NetSec BMR value, magic spell */
410 /* NetSec uses local RAM to handle GMAC desc arrays */
411 #define _RDLA 0x18000
412 #define _TDLA 0x1c000
413 /* lower address region is used for intermediate frame data buffers */
414
415 /*
416 * all below are software construction.
417 */
418 #define MD_NTXDESC 128
419 #define MD_NRXDESC 64
420
421 #define MD_NTXSEGS 16
422 #define MD_TXQUEUELEN 8
423 #define MD_TXQUEUELEN_MASK (MD_TXQUEUELEN - 1)
424 #define MD_TXQUEUE_GC (MD_TXQUEUELEN / 4)
425 #define MD_NTXDESC_MASK (MD_NTXDESC - 1)
426 #define MD_NEXTTX(x) (((x) + 1) & MD_NTXDESC_MASK)
427 #define MD_NEXTTXS(x) (((x) + 1) & MD_TXQUEUELEN_MASK)
428
429 #define MD_NRXDESC_MASK (MD_NRXDESC - 1)
430 #define MD_NEXTRX(x) (((x) + 1) & MD_NRXDESC_MASK)
431
432 struct control_data {
433 struct tdes cd_txdescs[MD_NTXDESC];
434 struct rdes cd_rxdescs[MD_NRXDESC];
435 };
436 #define SCX_CDOFF(x) offsetof(struct control_data, x)
437 #define SCX_CDTXOFF(x) SCX_CDOFF(cd_txdescs[(x)])
438 #define SCX_CDRXOFF(x) SCX_CDOFF(cd_rxdescs[(x)])
439
440 struct scx_txsoft {
441 struct mbuf *txs_mbuf; /* head of our mbuf chain */
442 bus_dmamap_t txs_dmamap; /* our DMA map */
443 int txs_firstdesc; /* first descriptor in packet */
444 int txs_lastdesc; /* last descriptor in packet */
445 int txs_ndesc; /* # of descriptors used */
446 };
447
448 struct scx_rxsoft {
449 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
450 bus_dmamap_t rxs_dmamap; /* our DMA map */
451 };
452
453 struct scx_softc {
454 device_t sc_dev; /* generic device information */
455 bus_space_tag_t sc_st; /* bus space tag */
456 bus_space_handle_t sc_sh; /* bus space handle */
457 bus_size_t sc_sz; /* csr map size */
458 bus_space_handle_t sc_eesh; /* eeprom section handle */
459 bus_size_t sc_eesz; /* eeprom map size */
460 bus_dma_tag_t sc_dmat; /* bus DMA tag */
461 struct ethercom sc_ethercom; /* Ethernet common data */
462 struct mii_data sc_mii; /* MII */
463 callout_t sc_callout; /* PHY monitor callout */
464 bus_dma_segment_t sc_seg; /* descriptor store seg */
465 int sc_nseg; /* descriptor store nseg */
466 void *sc_ih; /* interrupt cookie */
467 int sc_phy_id; /* PHY address */
468 int sc_flowflags; /* 802.3x PAUSE flow control */
469 uint32_t sc_mdclk; /* GAR 5:2 clock selection */
470 uint32_t sc_t0cotso; /* T0_CSUM | T0_TSO to run */
471 int sc_miigmii; /* 1: MII/GMII, 0: RGMII */
472 int sc_phandle; /* fdt phandle */
473 uint64_t sc_freq;
474 uint32_t sc_maxsize;
475
476 bus_dmamap_t sc_cddmamap; /* control data DMA map */
477 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
478
479 struct control_data *sc_control_data;
480 #define sc_txdescs sc_control_data->cd_txdescs
481 #define sc_rxdescs sc_control_data->cd_rxdescs
482
483 struct scx_txsoft sc_txsoft[MD_TXQUEUELEN];
484 struct scx_rxsoft sc_rxsoft[MD_NRXDESC];
485 int sc_txfree; /* number of free Tx descriptors */
486 int sc_txnext; /* next ready Tx descriptor */
487 int sc_txsfree; /* number of free Tx jobs */
488 int sc_txsnext; /* next ready Tx job */
489 int sc_txsdirty; /* dirty Tx jobs */
490 int sc_rxptr; /* next ready Rx descriptor/descsoft */
491
492 krndsource_t rnd_source; /* random source */
493 #ifdef GMAC_EVENT_COUNTERS
494 /* 80 event counters exist */
495 #endif
496 };
497
498 #define SCX_CDTXADDR(sc, x) ((sc)->sc_cddma + SCX_CDTXOFF((x)))
499 #define SCX_CDRXADDR(sc, x) ((sc)->sc_cddma + SCX_CDRXOFF((x)))
500
501 #define SCX_CDTXSYNC(sc, x, n, ops) \
502 do { \
503 int __x, __n; \
504 \
505 __x = (x); \
506 __n = (n); \
507 \
508 /* If it will wrap around, sync to the end of the ring. */ \
509 if ((__x + __n) > MD_NTXDESC) { \
510 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
511 SCX_CDTXOFF(__x), sizeof(struct tdes) * \
512 (MD_NTXDESC - __x), (ops)); \
513 __n -= (MD_NTXDESC - __x); \
514 __x = 0; \
515 } \
516 \
517 /* Now sync whatever is left. */ \
518 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
519 SCX_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \
520 } while (/*CONSTCOND*/0)
521
522 #define SCX_CDRXSYNC(sc, x, ops) \
523 do { \
524 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
525 SCX_CDRXOFF((x)), sizeof(struct rdes), (ops)); \
526 } while (/*CONSTCOND*/0)
527
528 #define SCX_INIT_RXDESC(sc, x) \
529 do { \
530 struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \
531 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \
532 struct mbuf *__m = __rxs->rxs_mbuf; \
533 bus_addr_t __p = __rxs->rxs_dmamap->dm_segs[0].ds_addr; \
534 bus_size_t __z = __rxs->rxs_dmamap->dm_segs[0].ds_len; \
535 __m->m_data = __m->m_ext.ext_buf; \
536 __rxd->r3 = htole32(__z - 4); \
537 __rxd->r2 = htole32(BUS_ADDR_LO32(__p)); \
538 __rxd->r1 = htole32(BUS_ADDR_HI32(__p)); \
539 __rxd->r0 &= htole32(R0_LD); \
540 __rxd->r0 |= htole32(R0_OWN); \
541 } while (/*CONSTCOND*/0)
542
543 /* memory mapped CSR register access */
544 #define CSR_READ(sc,off) \
545 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off))
546 #define CSR_WRITE(sc,off,val) \
547 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val))
548
549 /* flash memory access */
550 #define EE_READ(sc,off) \
551 bus_space_read_4((sc)->sc_st, (sc)->sc_eesh, (off))
552
553 static int scx_fdt_match(device_t, cfdata_t, void *);
554 static void scx_fdt_attach(device_t, device_t, void *);
555 static int scx_acpi_match(device_t, cfdata_t, void *);
556 static void scx_acpi_attach(device_t, device_t, void *);
557
558 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc),
559 scx_fdt_match, scx_fdt_attach, NULL, NULL);
560
561 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc),
562 scx_acpi_match, scx_acpi_attach, NULL, NULL);
563
564 static void scx_attach_i(struct scx_softc *);
565 static void scx_reset(struct scx_softc *);
566 static void scx_stop(struct ifnet *, int);
567 static int scx_init(struct ifnet *);
568 static int scx_ioctl(struct ifnet *, u_long, void *);
569 static void scx_set_rcvfilt(struct scx_softc *);
570 static void scx_start(struct ifnet *);
571 static void scx_watchdog(struct ifnet *);
572 static int scx_intr(void *);
573 static void txreap(struct scx_softc *);
574 static void rxfill(struct scx_softc *);
575 static int add_rxbuf(struct scx_softc *, int);
576 static void rxdrain(struct scx_softc *sc);
577 static void mii_statchg(struct ifnet *);
578 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
579 static int mii_readreg(device_t, int, int, uint16_t *);
580 static int mii_writereg(device_t, int, int, uint16_t);
581 static void phy_tick(void *);
582 static void dump_hwfeature(struct scx_softc *);
583
584 static void resetuengine(struct scx_softc *);
585 static void loaducode(struct scx_softc *);
586 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t);
587 static void forcephyloopback(struct scx_softc *);
588 static void resetphytonormal(struct scx_softc *);
589
590 static int get_mdioclk(uint32_t);
591
592 #define WAIT_FOR_SET(sc, reg, set) \
593 wait_for_bits(sc, reg, set, ~0, 0)
594 #define WAIT_FOR_CLR(sc, reg, clr) \
595 wait_for_bits(sc, reg, 0, clr, 0)
596
597 static int
wait_for_bits(struct scx_softc * sc,int reg,uint32_t set,uint32_t clr,uint32_t fail)598 wait_for_bits(struct scx_softc *sc, int reg,
599 uint32_t set, uint32_t clr, uint32_t fail)
600 {
601 uint32_t val;
602 int ntries;
603
604 for (ntries = 0; ntries < 1000; ntries++) {
605 val = CSR_READ(sc, reg);
606 if ((val & set) || !(val & clr))
607 return 0;
608 if (val & fail)
609 return 1;
610 DELAY(1);
611 }
612 return 1;
613 }
614
615 /* GMAC register indirect access */
616 static int
mac_read(struct scx_softc * sc,int reg)617 mac_read(struct scx_softc *sc, int reg)
618 {
619
620 CSR_WRITE(sc, MACCMD, reg | CMD_BUSY);
621 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY);
622 return CSR_READ(sc, MACDATA);
623 }
624
625 static void
mac_write(struct scx_softc * sc,int reg,int val)626 mac_write(struct scx_softc *sc, int reg, int val)
627 {
628
629 CSR_WRITE(sc, MACDATA, val);
630 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY);
631 (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY);
632 }
633
634 /* dig and decode "clock-frequency" value for a given clkname */
635 static int
get_clk_freq(int phandle,const char * clkname)636 get_clk_freq(int phandle, const char *clkname)
637 {
638 u_int index, n, cells;
639 const u_int *p;
640 int err, len, resid;
641 unsigned int freq = 0;
642
643 err = fdtbus_get_index(phandle, "clock-names", clkname, &index);
644 if (err == -1)
645 return -1;
646 p = fdtbus_get_prop(phandle, "clocks", &len);
647 if (p == NULL)
648 return -1;
649 for (n = 0, resid = len; resid > 0; n++) {
650 const int cc_phandle =
651 fdtbus_get_phandle_from_native(be32toh(p[0]));
652 if (of_getprop_uint32(cc_phandle, "#clock-cells", &cells))
653 return -1;
654 if (n == index) {
655 if (of_getprop_uint32(cc_phandle,
656 "clock-frequency", &freq))
657 return -1;
658 return freq;
659 }
660 resid -= (cells + 1) * 4;
661 p += (cells + 1) * 4;
662 }
663 return -1;
664 }
665
666 #define ATTACH_DEBUG 1
667
668 static const struct device_compatible_entry compat_data[] = {
669 { .compat = "socionext,synquacer-netsec" },
670 DEVICE_COMPAT_EOL
671 };
672 static const struct device_compatible_entry compatible[] = {
673 { .compat = "SCX0001" },
674 DEVICE_COMPAT_EOL
675 };
676
677 static int
scx_fdt_match(device_t parent,cfdata_t cf,void * aux)678 scx_fdt_match(device_t parent, cfdata_t cf, void *aux)
679 {
680 struct fdt_attach_args * const faa = aux;
681
682 return of_compatible_match(faa->faa_phandle, compat_data);
683 }
684
685 static void
scx_fdt_attach(device_t parent,device_t self,void * aux)686 scx_fdt_attach(device_t parent, device_t self, void *aux)
687 {
688 struct scx_softc * const sc = device_private(self);
689 struct fdt_attach_args * const faa = aux;
690 const int phandle = faa->faa_phandle;
691 bus_space_handle_t bsh;
692 bus_space_handle_t eebsh;
693 bus_addr_t addr[2];
694 bus_size_t size[2];
695 void *intrh;
696 char intrstr[128];
697 int phy_phandle;
698 const char *phy_mode;
699 bus_addr_t phy_id;
700 long ref_clk;
701
702 if (fdtbus_get_reg(phandle, 0, addr+0, size+0) != 0
703 || bus_space_map(faa->faa_bst, addr[0], size[0], 0, &bsh) != 0) {
704 aprint_error(": unable to map registers\n");
705 return;
706 }
707 if (fdtbus_get_reg(phandle, 1, addr+1, size+1) != 0
708 || bus_space_map(faa->faa_bst, addr[1], size[1], 0, &eebsh) != 0) {
709 aprint_error(": unable to map device eeprom\n");
710 goto fail;
711 }
712 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
713 aprint_error(": failed to decode interrupt\n");
714 goto fail;
715 }
716
717 phy_mode = fdtbus_get_string(phandle, "phy-mode");
718 if (phy_mode == NULL)
719 aprint_error(": missing 'phy-mode' property\n");
720 phy_phandle = fdtbus_get_phandle(phandle, "phy-handle");
721 if (phy_phandle == -1
722 || fdtbus_get_reg(phy_phandle, 0, &phy_id, NULL) != 0)
723 phy_id = MII_PHY_ANY;
724 ref_clk = get_clk_freq(phandle, "phy_ref_clk");
725 if (ref_clk == -1)
726 ref_clk = 250 * 1000 * 1000;
727
728 #if ATTACH_DEBUG == 1
729 aprint_normal("\n");
730 aprint_normal_dev(self,
731 "[FDT] phy mode %s, phy id %d, freq %ld\n",
732 phy_mode, (int)phy_id, ref_clk);
733 aprint_normal("%s", device_xname(self));
734 #endif
735
736 intrh = fdtbus_intr_establish(phandle, 0, IPL_NET,
737 NOT_MP_SAFE, scx_intr, sc);
738 if (intrh == NULL) {
739 aprint_error(": couldn't establish interrupt\n");
740 goto fail;
741 }
742 aprint_normal(" interrupt on %s", intrstr);
743
744 sc->sc_dev = self;
745 sc->sc_st = faa->faa_bst;
746 sc->sc_sh = bsh;
747 sc->sc_sz = size[0];
748 sc->sc_eesh = eebsh;
749 sc->sc_eesz = size[1];
750 sc->sc_ih = intrh;
751 sc->sc_dmat = faa->faa_dmat;
752 sc->sc_phandle = phandle;
753 sc->sc_phy_id = phy_id;
754 sc->sc_freq = ref_clk;
755
756 scx_attach_i(sc);
757
758 return;
759 fail:
760 if (sc->sc_eesz)
761 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz);
762 if (sc->sc_sz)
763 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
764 return;
765 }
766
767 static int
scx_acpi_match(device_t parent,cfdata_t cf,void * aux)768 scx_acpi_match(device_t parent, cfdata_t cf, void *aux)
769 {
770 struct acpi_attach_args *aa = aux;
771
772 return acpi_compatible_match(aa, compatible);
773 }
774
775 #define HWFEA_DEBUG 1
776
777 static void
scx_acpi_attach(device_t parent,device_t self,void * aux)778 scx_acpi_attach(device_t parent, device_t self, void *aux)
779 {
780 struct scx_softc * const sc = device_private(self);
781 struct acpi_attach_args * const aa = aux;
782 ACPI_HANDLE handle = aa->aa_node->ad_handle;
783 bus_space_handle_t bsh, eebsh;
784 struct acpi_resources res;
785 struct acpi_mem *mem, *mem1;
786 struct acpi_irq *irq;
787 ACPI_INTEGER max_spd, max_frame, phy_id, phy_freq;
788 ACPI_STATUS rv;
789 void *intrh;
790
791 rv = acpi_resource_parse(self, handle, "_CRS",
792 &res, &acpi_resource_parse_ops_default);
793 if (ACPI_FAILURE(rv))
794 return;
795 mem = acpi_res_mem(&res, 0);
796 irq = acpi_res_irq(&res, 0);
797 if (mem == NULL || irq == NULL || mem->ar_length == 0) {
798 aprint_error(": incomplete crs resources\n");
799 goto done;
800 }
801 if (bus_space_map(aa->aa_memt, mem->ar_base, mem->ar_length, 0,
802 &bsh) != 0) {
803 aprint_error(": unable to map registers\n");
804 goto done;
805 }
806 mem1 = acpi_res_mem(&res, 1); /* EEPROM for MAC address and ucode */
807 if (mem1 == NULL || mem1->ar_length == 0) {
808 aprint_error(": incomplete eeprom resources\n");
809 goto fail_0;
810 }
811 if (bus_space_map(aa->aa_memt, mem1->ar_base, mem1->ar_length, 0,
812 &eebsh)) {
813 aprint_error(": unable to map device eeprom\n");
814 goto fail_0;
815 }
816 rv = acpi_dsd_integer(handle, "max-speed", &max_spd);
817 if (ACPI_FAILURE(rv))
818 max_spd = 1000;
819 rv = acpi_dsd_integer(handle, "max-frame-size", &max_frame);
820 if (ACPI_FAILURE(rv))
821 max_frame = 2048;
822 rv = acpi_dsd_integer(handle, "phy-channel", &phy_id);
823 if (ACPI_FAILURE(rv))
824 phy_id = MII_PHY_ANY;
825 rv = acpi_dsd_integer(handle, "socionext,phy-clock-frequency",
826 &phy_freq);
827 if (ACPI_FAILURE(rv))
828 phy_freq = 250 * 1000 * 1000;
829
830 #if ATTACH_DEBUG == 1
831 aprint_normal_dev(self,
832 "[ACPI] max-speed %d, phy id %d, freq %ld\n",
833 (int)max_spd, (int)phy_id, phy_freq);
834 aprint_normal("%s", device_xname(self));
835 #endif
836
837 intrh = acpi_intr_establish(self, (uint64_t)(uintptr_t)handle,
838 IPL_NET, NOT_MP_SAFE, scx_intr, sc, device_xname(self));
839 if (intrh == NULL) {
840 aprint_error(": couldn't establish interrupt\n");
841 goto fail_1;
842 }
843
844 sc->sc_dev = self;
845 sc->sc_st = aa->aa_memt;
846 sc->sc_sh = bsh;
847 sc->sc_sz = mem->ar_length;
848 sc->sc_eesh = eebsh;
849 sc->sc_eesz = mem1->ar_length;
850 sc->sc_ih = intrh;
851 sc->sc_dmat =
852 BUS_DMA_TAG_VALID(aa->aa_dmat64) ? aa->aa_dmat64 : aa->aa_dmat;
853 sc->sc_phy_id = (int)phy_id;
854 sc->sc_freq = phy_freq;
855 sc->sc_maxsize = max_frame;
856
857 scx_attach_i(sc);
858 done:
859 acpi_resource_cleanup(&res);
860 return;
861 fail_1:
862 bus_space_unmap(sc->sc_st, sc->sc_eesh, sc->sc_eesz);
863 fail_0:
864 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
865 acpi_resource_cleanup(&res);
866 return;
867 }
868
869 static void
scx_attach_i(struct scx_softc * sc)870 scx_attach_i(struct scx_softc *sc)
871 {
872 struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
873 struct mii_data * const mii = &sc->sc_mii;
874 struct ifmedia * const ifm = &mii->mii_media;
875 uint32_t which, dwimp, dwfea;
876 uint8_t enaddr[ETHER_ADDR_LEN];
877 bus_dma_segment_t seg;
878 paddr_t p, q;
879 uint32_t csr;
880 int i, nseg, error = 0;
881
882 which = CSR_READ(sc, HWVER); /* Socionext version 5.xx */
883 dwimp = mac_read(sc, GMACIMPL); /* DWC implementation XX.YY */
884 dwfea = mac_read(sc, HWFEA); /* DWC feature bits */
885
886 aprint_naive("\n");
887 aprint_normal(": Socionext NetSec Gigabit Ethernet controller "
888 "%x.%x\n", which >> 16, which & 0xffff);
889
890 aprint_normal_dev(sc->sc_dev,
891 "DesignWare EMAC ver 0x%x (0x%x) hw feature %08x\n",
892 dwimp & 0xff, dwimp >> 8, dwfea);
893 dump_hwfeature(sc);
894
895 /* detected PHY type */
896 sc->sc_miigmii = ((dwfea & __BITS(30,28) >> 28) == 0);
897
898 /* fetch MAC address in flash 0:7, stored in big endian order */
899 csr = EE_READ(sc, 0x00);
900 enaddr[0] = csr >> 24;
901 enaddr[1] = csr >> 16;
902 enaddr[2] = csr >> 8;
903 enaddr[3] = csr;
904 csr = EE_READ(sc, 0x04);
905 enaddr[4] = csr >> 24;
906 enaddr[5] = csr >> 16;
907 aprint_normal_dev(sc->sc_dev,
908 "Ethernet address %s\n", ether_sprintf(enaddr));
909
910 sc->sc_mdclk = get_mdioclk(sc->sc_freq) << GAR_CLK; /* 5:2 clk ratio */
911
912 mii->mii_ifp = ifp;
913 mii->mii_readreg = mii_readreg;
914 mii->mii_writereg = mii_writereg;
915 mii->mii_statchg = mii_statchg;
916
917 sc->sc_ethercom.ec_mii = mii;
918 ifmedia_init(ifm, 0, ether_mediachange, scx_ifmedia_sts);
919 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id,
920 MII_OFFSET_ANY, MIIF_DOPAUSE);
921 if (LIST_FIRST(&mii->mii_phys) == NULL) {
922 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
923 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
924 } else
925 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
926 ifm->ifm_media = ifm->ifm_cur->ifm_media; /* as if user has requested */
927
928 /*
929 * Allocate the control data structures, and create and load the
930 * DMA map for it.
931 */
932 error = bus_dmamem_alloc(sc->sc_dmat,
933 sizeof(struct control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0);
934 if (error != 0) {
935 aprint_error_dev(sc->sc_dev,
936 "unable to allocate control data, error = %d\n", error);
937 goto fail_0;
938 }
939 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg,
940 sizeof(struct control_data), (void **)&sc->sc_control_data,
941 BUS_DMA_COHERENT);
942 if (error != 0) {
943 aprint_error_dev(sc->sc_dev,
944 "unable to map control data, error = %d\n", error);
945 goto fail_1;
946 }
947 error = bus_dmamap_create(sc->sc_dmat,
948 sizeof(struct control_data), 1,
949 sizeof(struct control_data), 0, 0, &sc->sc_cddmamap);
950 if (error != 0) {
951 aprint_error_dev(sc->sc_dev,
952 "unable to create control data DMA map, "
953 "error = %d\n", error);
954 goto fail_2;
955 }
956 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
957 sc->sc_control_data, sizeof(struct control_data), NULL, 0);
958 if (error != 0) {
959 aprint_error_dev(sc->sc_dev,
960 "unable to load control data DMA map, error = %d\n",
961 error);
962 goto fail_3;
963 }
964 for (i = 0; i < MD_TXQUEUELEN; i++) {
965 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
966 MD_NTXSEGS, MCLBYTES, 0, 0,
967 &sc->sc_txsoft[i].txs_dmamap)) != 0) {
968 aprint_error_dev(sc->sc_dev,
969 "unable to create tx DMA map %d, error = %d\n",
970 i, error);
971 goto fail_4;
972 }
973 }
974 for (i = 0; i < MD_NRXDESC; i++) {
975 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
976 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
977 aprint_error_dev(sc->sc_dev,
978 "unable to create rx DMA map %d, error = %d\n",
979 i, error);
980 goto fail_5;
981 }
982 sc->sc_rxsoft[i].rxs_mbuf = NULL;
983 }
984 sc->sc_seg = seg;
985 sc->sc_nseg = nseg;
986 #if 0
987 aprint_normal_dev(sc->sc_dev, "descriptor ds_addr %lx, ds_len %lx, nseg %d\n", seg.ds_addr, seg.ds_len, nseg);
988 #endif
989 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
990 ifp->if_softc = sc;
991 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
992 ifp->if_ioctl = scx_ioctl;
993 ifp->if_start = scx_start;
994 ifp->if_watchdog = scx_watchdog;
995 ifp->if_init = scx_init;
996 ifp->if_stop = scx_stop;
997 IFQ_SET_READY(&ifp->if_snd);
998
999 /* 802.1Q VLAN-sized frames, and 9000 jumbo frame are supported */
1000 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
1001 /* sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; not yet */
1002
1003 sc->sc_flowflags = 0; /* track PAUSE flow caps */
1004
1005 if_attach(ifp);
1006 if_deferred_start_init(ifp, NULL);
1007 ether_ifattach(ifp, enaddr);
1008
1009 callout_init(&sc->sc_callout, 0);
1010 callout_setfunc(&sc->sc_callout, phy_tick, sc);
1011
1012 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
1013 RND_TYPE_NET, RND_FLAG_DEFAULT);
1014
1015 resetuengine(sc);
1016 loaducode(sc);
1017
1018 /* feed NetSec descriptor array base addresses and timer value */
1019 p = SCX_CDTXADDR(sc, 0); /* tdes array (ring#0) */
1020 q = SCX_CDRXADDR(sc, 0); /* rdes array (ring#1) */
1021 CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(p));
1022 CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(p));
1023 CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(q));
1024 CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(q));
1025 CSR_WRITE(sc, TXCONF, DESCNF_LE); /* little endian */
1026 CSR_WRITE(sc, RXCONF, DESCNF_LE); /* little endian */
1027 CSR_WRITE(sc, DMACTL_TMR, sc->sc_freq / 1000000 - 1);
1028
1029 forcephyloopback(sc);/* make PHY loopback mode for uengine init */
1030
1031 CSR_WRITE(sc, xINTSR, IRQ_UCODE); /* pre-cautional W1C */
1032 CSR_WRITE(sc, CORESTAT, 0); /* start uengine to reprogram */
1033 error = WAIT_FOR_SET(sc, xINTSR, IRQ_UCODE);
1034 if (error) {
1035 aprint_error_dev(sc->sc_dev, "uengine start failed\n");
1036 }
1037 CSR_WRITE(sc, xINTSR, IRQ_UCODE); /* W1C load complete report */
1038
1039 resetphytonormal(sc); /* take back PHY to normal mode */
1040
1041 CSR_WRITE(sc, DMACTL_M2H, M2H_MODE_TRANS);
1042 CSR_WRITE(sc, PKTCTRL, MODENRM); /* change to use normal mode */
1043 error = WAIT_FOR_SET(sc, MODE_TRANS, T2N_DONE);
1044 if (error) {
1045 aprint_error_dev(sc->sc_dev, "uengine mode change failed\n");
1046 }
1047
1048 CSR_WRITE(sc, TXISR, ~0); /* clear pending emtpry/error irq */
1049 CSR_WRITE(sc, xINTAE_CLR, ~0); /* disable tx / rx interrupts */
1050
1051 return;
1052
1053 fail_5:
1054 for (i = 0; i < MD_NRXDESC; i++) {
1055 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
1056 bus_dmamap_destroy(sc->sc_dmat,
1057 sc->sc_rxsoft[i].rxs_dmamap);
1058 }
1059 fail_4:
1060 for (i = 0; i < MD_TXQUEUELEN; i++) {
1061 if (sc->sc_txsoft[i].txs_dmamap != NULL)
1062 bus_dmamap_destroy(sc->sc_dmat,
1063 sc->sc_txsoft[i].txs_dmamap);
1064 }
1065 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
1066 fail_3:
1067 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
1068 fail_2:
1069 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
1070 sizeof(struct control_data));
1071 fail_1:
1072 bus_dmamem_free(sc->sc_dmat, &seg, nseg);
1073 fail_0:
1074 if (sc->sc_phandle)
1075 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih);
1076 else
1077 acpi_intr_disestablish(sc->sc_ih);
1078 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
1079 return;
1080 }
1081
1082 static void
scx_reset(struct scx_softc * sc)1083 scx_reset(struct scx_softc *sc)
1084 {
1085 int loop = 0, busy;
1086
1087 mac_write(sc, GMACOMR, 0);
1088 mac_write(sc, GMACBMR, BMR_RST);
1089 do {
1090 DELAY(1);
1091 busy = mac_read(sc, GMACBMR) & BMR_RST;
1092 } while (++loop < 3000 && busy);
1093 mac_write(sc, GMACBMR, _BMR);
1094 mac_write(sc, GMACAFR, 0);
1095 }
1096
1097 static void
scx_stop(struct ifnet * ifp,int disable)1098 scx_stop(struct ifnet *ifp, int disable)
1099 {
1100 struct scx_softc *sc = ifp->if_softc;
1101 uint32_t csr;
1102
1103 /* Stop the one second clock. */
1104 callout_stop(&sc->sc_callout);
1105
1106 /* Down the MII. */
1107 mii_down(&sc->sc_mii);
1108
1109 /* Mark the interface down and cancel the watchdog timer. */
1110 ifp->if_flags &= ~IFF_RUNNING;
1111 ifp->if_timer = 0;
1112
1113 CSR_WRITE(sc, RXIE_CLR, ~0);
1114 CSR_WRITE(sc, TXIE_CLR, ~0);
1115 CSR_WRITE(sc, xINTAE_CLR, ~0);
1116 CSR_WRITE(sc, TXISR, ~0);
1117 CSR_WRITE(sc, RXISR, ~0);
1118
1119 csr = mac_read(sc, GMACOMR);
1120 mac_write(sc, GMACOMR, csr &~ (OMR_SR | OMR_ST));
1121 }
1122
1123 static int
scx_init(struct ifnet * ifp)1124 scx_init(struct ifnet *ifp)
1125 {
1126 struct scx_softc *sc = ifp->if_softc;
1127 const uint8_t *ea = CLLADDR(ifp->if_sadl);
1128 uint32_t csr;
1129 int i, error;
1130
1131 /* Cancel pending I/O. */
1132 scx_stop(ifp, 0);
1133
1134 /* Reset the chip to a known state. */
1135 scx_reset(sc);
1136
1137 /* build sane Tx */
1138 memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC);
1139 sc->sc_txdescs[MD_NTXDESC - 1].t0 = htole32(T0_LD); /* tie off */
1140 SCX_CDTXSYNC(sc, 0, MD_NTXDESC,
1141 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1142 sc->sc_txfree = MD_NTXDESC;
1143 sc->sc_txnext = 0;
1144 for (i = 0; i < MD_TXQUEUELEN; i++)
1145 sc->sc_txsoft[i].txs_mbuf = NULL;
1146 sc->sc_txsfree = MD_TXQUEUELEN;
1147 sc->sc_txsnext = 0;
1148 sc->sc_txsdirty = 0;
1149
1150 /* load Rx descriptors with fresh mbuf */
1151 for (i = 0; i < MD_NRXDESC; i++) {
1152 if (sc->sc_rxsoft[i].rxs_mbuf == NULL) {
1153 if ((error = add_rxbuf(sc, i)) != 0) {
1154 aprint_error_dev(sc->sc_dev,
1155 "unable to allocate or map rx "
1156 "buffer %d, error = %d\n",
1157 i, error);
1158 rxdrain(sc);
1159 goto out;
1160 }
1161 }
1162 else
1163 SCX_INIT_RXDESC(sc, i);
1164 }
1165 sc->sc_rxdescs[MD_NRXDESC - 1].r0 = htole32(R0_LD); /* tie off */
1166 sc->sc_rxptr = 0;
1167
1168 /* set my address in perfect match slot 0. little endian order */
1169 csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0];
1170 mac_write(sc, GMACMAL0, csr);
1171 csr = (ea[5] << 8) | ea[4];
1172 mac_write(sc, GMACMAH0, csr);
1173
1174 /* accept multicast frame or run promisc mode */
1175 scx_set_rcvfilt(sc);
1176
1177 /* set current media */
1178 if ((error = ether_mediachange(ifp)) != 0)
1179 goto out;
1180
1181 CSR_WRITE(sc, DESC_SRST, 01);
1182 WAIT_FOR_CLR(sc, DESC_SRST, 01);
1183
1184 CSR_WRITE(sc, DESC_INIT, 01);
1185 WAIT_FOR_CLR(sc, DESC_INIT, 01);
1186
1187 /* feed local memory descriptor array base addresses */
1188 mac_write(sc, GMACRDLA, _RDLA); /* GMAC rdes store */
1189 mac_write(sc, GMACTDLA, _TDLA); /* GMAC tdes store */
1190
1191 CSR_WRITE(sc, FLOWTHR, (48<<16) | 36); /* pause|resume threshold */
1192 mac_write(sc, GMACFCR, 256 << 16); /* 31:16 pause value */
1193
1194 CSR_WRITE(sc, INTF_SEL, sc->sc_miigmii ? INTF_GMII : INTF_RGMII);
1195
1196 CSR_WRITE(sc, RXCOALESC, 8); /* Rx coalesce bound */
1197 CSR_WRITE(sc, TXCOALESC, 8); /* Tx coalesce bound */
1198 CSR_WRITE(sc, RCLSCTIME, 500); /* Rx co. guard time usec */
1199 CSR_WRITE(sc, TCLSCTIME, 500); /* Tx co. guard time usec */
1200
1201 CSR_WRITE(sc, RXIE_SET, RXI_RC_ERR | RXI_PKTCNT | RXI_TMREXP);
1202 CSR_WRITE(sc, TXIE_SET, TXI_TR_ERR | TXI_TXDONE | TXI_TMREXP);
1203 CSR_WRITE(sc, xINTAE_SET, IRQ_RX | IRQ_TX);
1204 #if 1
1205 /* clear event counters, auto-zero after every read */
1206 mac_write(sc, GMACEVCTL, EVC_CR | EVC_ROR);
1207 #endif
1208 /* kick to start GMAC engine */
1209 csr = mac_read(sc, GMACOMR);
1210 mac_write(sc, GMACOMR, csr | OMR_SR | OMR_ST);
1211
1212 ifp->if_flags |= IFF_RUNNING;
1213
1214 /* start one second timer */
1215 callout_schedule(&sc->sc_callout, hz);
1216 out:
1217 return error;
1218 }
1219
1220 static int
scx_ioctl(struct ifnet * ifp,u_long cmd,void * data)1221 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1222 {
1223 struct scx_softc *sc = ifp->if_softc;
1224 struct ifreq *ifr = (struct ifreq *)data;
1225 struct ifmedia *ifm = &sc->sc_mii.mii_media;
1226 int s, error;
1227
1228 s = splnet();
1229
1230 switch (cmd) {
1231 case SIOCSIFMEDIA:
1232 /* Flow control requires full-duplex mode. */
1233 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
1234 (ifr->ifr_media & IFM_FDX) == 0)
1235 ifr->ifr_media &= ~IFM_ETH_FMASK;
1236 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
1237 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
1238 /* We can do both TXPAUSE and RXPAUSE. */
1239 ifr->ifr_media |=
1240 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
1241 }
1242 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
1243 }
1244 error = ifmedia_ioctl(ifp, ifr, ifm, cmd);
1245 break;
1246 default:
1247 error = ether_ioctl(ifp, cmd, data);
1248 if (error != ENETRESET)
1249 break;
1250 error = 0;
1251 if (cmd == SIOCSIFCAP)
1252 error = if_init(ifp);
1253 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
1254 ;
1255 else if (ifp->if_flags & IFF_RUNNING) {
1256 /*
1257 * Multicast list has changed; set the hardware filter
1258 * accordingly.
1259 */
1260 scx_set_rcvfilt(sc);
1261 }
1262 break;
1263 }
1264
1265 splx(s);
1266 return error;
1267 }
1268
1269 static uint32_t
bit_reverse_32(uint32_t x)1270 bit_reverse_32(uint32_t x)
1271 {
1272 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
1273 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
1274 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
1275 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
1276 return (x >> 16) | (x << 16);
1277 }
1278
1279 #define MCAST_DEBUG 0
1280
1281 static void
scx_set_rcvfilt(struct scx_softc * sc)1282 scx_set_rcvfilt(struct scx_softc *sc)
1283 {
1284 struct ethercom * const ec = &sc->sc_ethercom;
1285 struct ifnet * const ifp = &ec->ec_if;
1286 struct ether_multistep step;
1287 struct ether_multi *enm;
1288 uint32_t mchash[2]; /* 2x 32 = 64 bit */
1289 uint32_t csr, crc;
1290 int i;
1291
1292 csr = mac_read(sc, GMACAFR);
1293 csr &= ~(AFR_PR | AFR_PM | AFR_MHTE | AFR_HPF);
1294 mac_write(sc, GMACAFR, csr);
1295
1296 /* clear 15 entry supplemental perfect match filter */
1297 for (i = 1; i < 16; i++)
1298 mac_write(sc, GMACMAH(i), 0);
1299 /* build 64 bit multicast hash filter */
1300 crc = mchash[1] = mchash[0] = 0;
1301
1302 ETHER_LOCK(ec);
1303 if (ifp->if_flags & IFF_PROMISC) {
1304 ec->ec_flags |= ETHER_F_ALLMULTI;
1305 ETHER_UNLOCK(ec);
1306 /* run promisc. mode */
1307 csr |= AFR_PR;
1308 goto update;
1309 }
1310 ec->ec_flags &= ~ETHER_F_ALLMULTI;
1311 ETHER_FIRST_MULTI(step, ec, enm);
1312 i = 1; /* slot 0 is occupied */
1313 while (enm != NULL) {
1314 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1315 /*
1316 * We must listen to a range of multicast addresses.
1317 * For now, just accept all multicasts, rather than
1318 * trying to set only those filter bits needed to match
1319 * the range. (At this time, the only use of address
1320 * ranges is for IP multicast routing, for which the
1321 * range is big enough to require all bits set.)
1322 */
1323 ec->ec_flags |= ETHER_F_ALLMULTI;
1324 ETHER_UNLOCK(ec);
1325 /* accept all multi */
1326 csr |= AFR_PM;
1327 goto update;
1328 }
1329 #if MCAST_DEBUG == 1
1330 aprint_normal_dev(sc->sc_dev, "[%d] %s\n", i, ether_sprintf(enm->enm_addrlo));
1331 #endif
1332 if (i < 16) {
1333 /* use 15 entry perfect match filter */
1334 uint32_t addr;
1335 uint8_t *ep = enm->enm_addrlo;
1336 addr = (ep[3] << 24) | (ep[2] << 16)
1337 | (ep[1] << 8) | ep[0];
1338 mac_write(sc, GMACMAL(i), addr);
1339 addr = (ep[5] << 8) | ep[4];
1340 mac_write(sc, GMACMAH(i), addr | 1U<<31);
1341 } else {
1342 /* use hash table when too many */
1343 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1344 crc = bit_reverse_32(~crc);
1345 /* 1(31) 5(30:26) bit sampling */
1346 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
1347 }
1348 ETHER_NEXT_MULTI(step, enm);
1349 i++;
1350 }
1351 ETHER_UNLOCK(ec);
1352 if (crc)
1353 csr |= AFR_MHTE; /* use mchash[] */
1354 csr |= AFR_HPF; /* use perfect match as well */
1355 update:
1356 mac_write(sc, GMACMHTH, mchash[1]);
1357 mac_write(sc, GMACMHTL, mchash[0]);
1358 mac_write(sc, GMACAFR, csr);
1359 return;
1360 }
1361
1362 static void
scx_start(struct ifnet * ifp)1363 scx_start(struct ifnet *ifp)
1364 {
1365 struct scx_softc *sc = ifp->if_softc;
1366 struct mbuf *m0;
1367 struct scx_txsoft *txs;
1368 bus_dmamap_t dmamap;
1369 int error, nexttx, lasttx, ofree, seg;
1370 uint32_t tdes0;
1371
1372 if ((ifp->if_flags & IFF_RUNNING) == 0)
1373 return;
1374
1375 /* Remember the previous number of free descriptors. */
1376 ofree = sc->sc_txfree;
1377 /*
1378 * Loop through the send queue, setting up transmit descriptors
1379 * until we drain the queue, or use up all available transmit
1380 * descriptors.
1381 */
1382 for (;;) {
1383 IFQ_POLL(&ifp->if_snd, m0);
1384 if (m0 == NULL)
1385 break;
1386 if (sc->sc_txsfree < MD_TXQUEUE_GC) {
1387 txreap(sc);
1388 if (sc->sc_txsfree == 0)
1389 break;
1390 }
1391 txs = &sc->sc_txsoft[sc->sc_txsnext];
1392 dmamap = txs->txs_dmamap;
1393 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
1394 BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1395 if (error) {
1396 if (error == EFBIG) {
1397 aprint_error_dev(sc->sc_dev,
1398 "Tx packet consumes too many "
1399 "DMA segments, dropping...\n");
1400 IFQ_DEQUEUE(&ifp->if_snd, m0);
1401 m_freem(m0);
1402 if_statinc(ifp, if_oerrors);
1403 continue;
1404 }
1405 /* Short on resources, just stop for now. */
1406 break;
1407 }
1408 if (dmamap->dm_nsegs > sc->sc_txfree) {
1409 /*
1410 * Not enough free descriptors to transmit this
1411 * packet. We haven't committed anything yet,
1412 * so just unload the DMA map, put the packet
1413 * back on the queue, and punt.
1414 */
1415 bus_dmamap_unload(sc->sc_dmat, dmamap);
1416 break;
1417 }
1418
1419 IFQ_DEQUEUE(&ifp->if_snd, m0);
1420 /*
1421 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
1422 */
1423 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
1424 BUS_DMASYNC_PREWRITE);
1425
1426 tdes0 = 0; /* to postpone 1st segment T0_OWN write */
1427 lasttx = -1;
1428 for (nexttx = sc->sc_txnext, seg = 0;
1429 seg < dmamap->dm_nsegs;
1430 seg++, nexttx = MD_NEXTTX(nexttx)) {
1431 struct tdes *tdes = &sc->sc_txdescs[nexttx];
1432 bus_addr_t p = dmamap->dm_segs[seg].ds_addr;
1433 bus_size_t z = dmamap->dm_segs[seg].ds_len;
1434 /*
1435 * If this is the first descriptor we're
1436 * enqueueing, don't set the OWN bit just
1437 * yet. That could cause a race condition.
1438 * We'll do it below.
1439 */
1440 tdes->t3 = htole32(z);
1441 tdes->t2 = htole32(BUS_ADDR_LO32(p));
1442 tdes->t1 = htole32(BUS_ADDR_HI32(p));
1443 tdes->t0 &= htole32(T0_LD);
1444 tdes->t0 |= htole32(tdes0 |
1445 (15 << T0_TDRID) | T0_PT |
1446 sc->sc_t0cotso | T0_TRS);
1447 tdes0 = T0_OWN; /* 2nd and other segments */
1448 /* NB; t0 DRID field contains zero */
1449 lasttx = nexttx;
1450 }
1451
1452 /* HW lacks of per-frame xmit done interrupt control */
1453
1454 /* Write deferred 1st segment T0_OWN at the final stage */
1455 sc->sc_txdescs[lasttx].t0 |= htole32(T0_LS);
1456 sc->sc_txdescs[sc->sc_txnext].t0 |= htole32(T0_FS | T0_OWN);
1457 SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
1458 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1459
1460 /* submit one frame to xmit */
1461 CSR_WRITE(sc, TXSUBMIT, 1);
1462
1463 txs->txs_mbuf = m0;
1464 txs->txs_firstdesc = sc->sc_txnext;
1465 txs->txs_lastdesc = lasttx;
1466 txs->txs_ndesc = dmamap->dm_nsegs;
1467 sc->sc_txfree -= txs->txs_ndesc;
1468 sc->sc_txnext = nexttx;
1469 sc->sc_txsfree--;
1470 sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext);
1471 /*
1472 * Pass the packet to any BPF listeners.
1473 */
1474 bpf_mtap(ifp, m0, BPF_D_OUT);
1475 }
1476 if (sc->sc_txfree != ofree) {
1477 /* Set a watchdog timer in case the chip flakes out. */
1478 ifp->if_timer = 5;
1479 }
1480 }
1481
1482 #define EVENT_DEBUG 1
1483
1484 static void
scx_watchdog(struct ifnet * ifp)1485 scx_watchdog(struct ifnet *ifp)
1486 {
1487 struct scx_softc *sc = ifp->if_softc;
1488
1489 /*
1490 * Since we're not interrupting every packet, sweep
1491 * up before we report an error.
1492 */
1493 txreap(sc);
1494
1495 if (sc->sc_txfree != MD_NTXDESC) {
1496 aprint_error_dev(sc->sc_dev,
1497 "device timeout (txfree %d txsfree %d txnext %d)\n",
1498 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext);
1499 if_statinc(ifp, if_oerrors);
1500 #if EVENT_DEBUG == 1
1501 aprint_error_dev(sc->sc_dev,
1502 "tx frames %d, octects %d, bcast %d, mcast %d\n",
1503 mac_read(sc, GMACEVCNT(1)),
1504 mac_read(sc, GMACEVCNT(0)),
1505 mac_read(sc, GMACEVCNT(2)),
1506 mac_read(sc, GMACEVCNT(3)));
1507 aprint_error_dev(sc->sc_dev,
1508 "rx frames %d, octects %d, bcast %d, mcast %d\n",
1509 mac_read(sc, GMACEVCNT(27)),
1510 mac_read(sc, GMACEVCNT(28)),
1511 mac_read(sc, GMACEVCNT(30)),
1512 mac_read(sc, GMACEVCNT(31)));
1513 aprint_error_dev(sc->sc_dev,
1514 "current tdes addr %x, buf addr %x\n",
1515 mac_read(sc, 0x1048), mac_read(sc, 0x1050));
1516 aprint_error_dev(sc->sc_dev,
1517 "current rdes addr %x, buf addr %x\n",
1518 mac_read(sc, 0x104c), mac_read(sc, 0x1054));
1519 #endif
1520 /* Reset the interface. */
1521 scx_init(ifp);
1522 }
1523
1524 scx_start(ifp);
1525 }
1526
1527 static int
scx_intr(void * arg)1528 scx_intr(void *arg)
1529 {
1530 struct scx_softc *sc = arg;
1531 uint32_t enable, status;
1532
1533 status = CSR_READ(sc, xINTSR); /* not W1C */
1534 enable = CSR_READ(sc, xINTAEN);
1535 if ((status & enable) == 0)
1536 return 0;
1537 if (status & (IRQ_TX | IRQ_RX)) {
1538 CSR_WRITE(sc, xINTAE_CLR, (IRQ_TX | IRQ_RX));
1539
1540 status = CSR_READ(sc, RXISR);
1541 CSR_WRITE(sc, RXISR, status);
1542 if (status & RXI_RC_ERR)
1543 aprint_error_dev(sc->sc_dev, "Rx error\n");
1544 if (status & (RXI_PKTCNT | RXI_TMREXP)) {
1545 rxfill(sc);
1546 (void)CSR_READ(sc, RXAVAILCNT); /* clear IRQ_RX ? */
1547 }
1548
1549 status = CSR_READ(sc, TXISR);
1550 CSR_WRITE(sc, TXISR, status);
1551 if (status & TXI_TR_ERR)
1552 aprint_error_dev(sc->sc_dev, "Tx error\n");
1553 if (status & (TXI_TXDONE | TXI_TMREXP)) {
1554 txreap(sc);
1555 (void)CSR_READ(sc, TXDONECNT); /* clear IRQ_TX ? */
1556 }
1557
1558 CSR_WRITE(sc, xINTAE_SET, (IRQ_TX | IRQ_RX));
1559 }
1560 return 1;
1561 }
1562
1563 static void
txreap(struct scx_softc * sc)1564 txreap(struct scx_softc *sc)
1565 {
1566 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1567 struct scx_txsoft *txs;
1568 uint32_t txstat;
1569 int i;
1570
1571 for (i = sc->sc_txsdirty; sc->sc_txsfree != MD_TXQUEUELEN;
1572 i = MD_NEXTTXS(i), sc->sc_txsfree++) {
1573 txs = &sc->sc_txsoft[i];
1574
1575 SCX_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc,
1576 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1577
1578 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].t0);
1579 if (txstat & T0_OWN) /* desc is still in use */
1580 break;
1581
1582 /* There is no way to tell transmission status per frame */
1583
1584 if_statinc(ifp, if_opackets);
1585
1586 sc->sc_txfree += txs->txs_ndesc;
1587 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
1588 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1589 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
1590 m_freem(txs->txs_mbuf);
1591 txs->txs_mbuf = NULL;
1592 }
1593 sc->sc_txsdirty = i;
1594 if (sc->sc_txsfree == MD_TXQUEUELEN)
1595 ifp->if_timer = 0;
1596 }
1597
1598 static void
rxfill(struct scx_softc * sc)1599 rxfill(struct scx_softc *sc)
1600 {
1601 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1602 struct scx_rxsoft *rxs;
1603 struct mbuf *m;
1604 uint32_t rxstat, rlen;
1605 int i;
1606
1607 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) {
1608 SCX_CDRXSYNC(sc, i,
1609 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1610
1611 rxstat = le32toh(sc->sc_rxdescs[i].r0);
1612 if (rxstat & R0_OWN) /* desc is left empty */
1613 break;
1614
1615 /* received frame length in R3 31:16 */
1616 rlen = le32toh(sc->sc_rxdescs[i].r3) >> 16;
1617
1618 /* R0_FS | R0_LS must have been marked for this desc */
1619 rxs = &sc->sc_rxsoft[i];
1620 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1621 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1622
1623 /* dispense new storage to receive frame */
1624 m = rxs->rxs_mbuf;
1625 if (add_rxbuf(sc, i) != 0) {
1626 if_statinc(ifp, if_ierrors); /* resource shortage */
1627 SCX_INIT_RXDESC(sc, i); /* then reuse */
1628 bus_dmamap_sync(sc->sc_dmat,
1629 rxs->rxs_dmamap, 0,
1630 rxs->rxs_dmamap->dm_mapsize,
1631 BUS_DMASYNC_PREREAD);
1632 continue;
1633 }
1634 /* complete mbuf */
1635 m_set_rcvif(m, ifp);
1636 m->m_pkthdr.len = m->m_len = rlen;
1637 m->m_flags |= M_HASFCS;
1638 if (rxstat & R0_CSUM) {
1639 uint32_t csum = M_CSUM_IPv4;
1640 if (rxstat & R0_CERR)
1641 csum |= M_CSUM_IPv4_BAD;
1642 m->m_pkthdr.csum_flags |= csum;
1643 }
1644 /* and pass to upper layer */
1645 if_percpuq_enqueue(ifp->if_percpuq, m);
1646 }
1647 sc->sc_rxptr = i;
1648 }
1649
1650 static int
add_rxbuf(struct scx_softc * sc,int i)1651 add_rxbuf(struct scx_softc *sc, int i)
1652 {
1653 struct scx_rxsoft *rxs = &sc->sc_rxsoft[i];
1654 struct mbuf *m;
1655 int error;
1656
1657 MGETHDR(m, M_DONTWAIT, MT_DATA);
1658 if (m == NULL)
1659 return ENOBUFS;
1660 MCLGET(m, M_DONTWAIT);
1661 if ((m->m_flags & M_EXT) == 0) {
1662 m_freem(m);
1663 return ENOBUFS;
1664 }
1665 if (rxs->rxs_mbuf != NULL)
1666 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1667 rxs->rxs_mbuf = m;
1668 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
1669 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
1670 if (error) {
1671 aprint_error_dev(sc->sc_dev,
1672 "can't load rx DMA map %d, error = %d\n", i, error);
1673 panic("add_rxbuf");
1674 }
1675 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1676 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1677 SCX_INIT_RXDESC(sc, i);
1678
1679 return 0;
1680 }
1681
1682 static void
rxdrain(struct scx_softc * sc)1683 rxdrain(struct scx_softc *sc)
1684 {
1685 struct scx_rxsoft *rxs;
1686 int i;
1687
1688 for (i = 0; i < MD_NRXDESC; i++) {
1689 rxs = &sc->sc_rxsoft[i];
1690 if (rxs->rxs_mbuf != NULL) {
1691 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1692 m_freem(rxs->rxs_mbuf);
1693 rxs->rxs_mbuf = NULL;
1694 }
1695 }
1696 }
1697
1698 #define LINK_DEBUG 0
1699
1700 static void
mii_statchg(struct ifnet * ifp)1701 mii_statchg(struct ifnet *ifp)
1702 {
1703 struct scx_softc *sc = ifp->if_softc;
1704 struct mii_data *mii = &sc->sc_mii;
1705 const int Mbps[4] = { 10, 100, 1000, 0 };
1706 uint32_t miisr, mcr, fcr;
1707 int spd;
1708
1709 /* decode MIISR register value */
1710 miisr = mac_read(sc, GMACMIISR);
1711 spd = Mbps[(miisr & MIISR_SPD) >> 1];
1712 #if LINK_DEBUG == 1
1713 static uint32_t oldmiisr = 0;
1714 if (miisr != oldmiisr) {
1715 printf("MII link status (0x%x) %s",
1716 miisr, (miisr & MIISR_LUP) ? "up" : "down");
1717 if (miisr & MIISR_LUP) {
1718 printf(" spd%d", spd);
1719 if (miisr & MIISR_FDX)
1720 printf(",full-duplex");
1721 }
1722 printf("\n");
1723 }
1724 #endif
1725 /* Get flow control negotiation result. */
1726 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
1727 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags)
1728 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
1729
1730 /* Adjust speed 1000/100/10. */
1731 mcr = mac_read(sc, GMACMCR) &~ (MCR_PS | MCR_FES);
1732 if (sc->sc_miigmii) {
1733 if (spd != 1000)
1734 mcr |= MCR_PS;
1735 } else {
1736 if (spd == 100)
1737 mcr |= MCR_FES;
1738 }
1739 mcr |= MCR_CST | MCR_JE;
1740 if (sc->sc_miigmii == 0)
1741 mcr |= MCR_IBN;
1742
1743 /* Adjust duplexity and PAUSE flow control. */
1744 mcr &= ~MCR_USEFDX;
1745 fcr = mac_read(sc, GMACFCR) & ~(FCR_TFE | FCR_RFE);
1746 if (miisr & MIISR_FDX) {
1747 if (sc->sc_flowflags & IFM_ETH_TXPAUSE)
1748 fcr |= FCR_TFE;
1749 if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
1750 fcr |= FCR_RFE;
1751 mcr |= MCR_USEFDX;
1752 }
1753 mac_write(sc, GMACMCR, mcr);
1754 mac_write(sc, GMACFCR, fcr);
1755 #if LINK_DEBUG == 1
1756 if (miisr != oldmiisr) {
1757 printf("%ctxfe, %crxfe\n",
1758 (fcr & FCR_TFE) ? '+' : '-',
1759 (fcr & FCR_RFE) ? '+' : '-');
1760 }
1761 oldmiisr = miisr;
1762 #endif
1763 }
1764
1765 static void
scx_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1766 scx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1767 {
1768 struct scx_softc *sc = ifp->if_softc;
1769 struct mii_data *mii = &sc->sc_mii;
1770
1771 mii_pollstat(mii);
1772 ifmr->ifm_status = mii->mii_media_status;
1773 ifmr->ifm_active = sc->sc_flowflags |
1774 (mii->mii_media_active & ~IFM_ETH_FMASK);
1775 }
1776
1777 static int
mii_readreg(device_t self,int phy,int reg,uint16_t * val)1778 mii_readreg(device_t self, int phy, int reg, uint16_t *val)
1779 {
1780 struct scx_softc *sc = device_private(self);
1781 uint32_t miia;
1782 int ntries;
1783
1784 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk;
1785 mac_write(sc, GMACGAR, miia | GAR_BUSY);
1786 for (ntries = 0; ntries < 1000; ntries++) {
1787 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0)
1788 goto unbusy;
1789 DELAY(1);
1790 }
1791 return ETIMEDOUT;
1792 unbusy:
1793 *val = mac_read(sc, GMACGDR);
1794 return 0;
1795 }
1796
1797 static int
mii_writereg(device_t self,int phy,int reg,uint16_t val)1798 mii_writereg(device_t self, int phy, int reg, uint16_t val)
1799 {
1800 struct scx_softc *sc = device_private(self);
1801 uint32_t miia;
1802 uint16_t dummy;
1803 int ntries;
1804
1805 miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk;
1806 mac_write(sc, GMACGDR, val);
1807 mac_write(sc, GMACGAR, miia | GAR_IOWR | GAR_BUSY);
1808 for (ntries = 0; ntries < 1000; ntries++) {
1809 if ((mac_read(sc, GMACGAR) & GAR_BUSY) == 0)
1810 goto unbusy;
1811 DELAY(1);
1812 }
1813 return ETIMEDOUT;
1814 unbusy:
1815 mii_readreg(self, phy, MII_PHYIDR1, &dummy); /* dummy read cycle */
1816 return 0;
1817 }
1818
1819 static void
phy_tick(void * arg)1820 phy_tick(void *arg)
1821 {
1822 struct scx_softc *sc = arg;
1823 struct mii_data *mii = &sc->sc_mii;
1824 int s;
1825
1826 s = splnet();
1827 mii_tick(mii);
1828 splx(s);
1829 #ifdef GMAC_EVENT_COUNTERS
1830 /* 80 event counters exist */
1831 #endif
1832 callout_schedule(&sc->sc_callout, hz);
1833 }
1834
1835 static void
resetuengine(struct scx_softc * sc)1836 resetuengine(struct scx_softc *sc)
1837 {
1838
1839 if (CSR_READ(sc, CORESTAT) == 0) {
1840 /* make sure to stop */
1841 CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP);
1842 CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP);
1843 WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP);
1844 WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP);
1845 }
1846 CSR_WRITE(sc, SWRESET, 0); /* reset operation */
1847 CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */
1848 CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS);
1849 WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS));
1850 }
1851
1852 #define UCODE_DEBUG 0
1853
1854 /*
1855 * 3 independent uengines exist to process host2media, media2host and
1856 * packet data flows.
1857 */
1858 static void
loaducode(struct scx_softc * sc)1859 loaducode(struct scx_softc *sc)
1860 {
1861 uint32_t up, lo, sz;
1862 uint64_t addr;
1863
1864 up = EE_READ(sc, 0x08); /* H->M ucode addr high */
1865 lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */
1866 sz = EE_READ(sc, 0x10); /* H->M ucode size */
1867 sz *= 4;
1868 addr = ((uint64_t)up << 32) | lo;
1869 injectucode(sc, UCODE_H2M, (bus_addr_t)addr, (bus_size_t)sz);
1870 #if UCODE_DEBUG == 1
1871 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz);
1872 #endif
1873
1874 up = EE_READ(sc, 0x14); /* M->H ucode addr high */
1875 lo = EE_READ(sc, 0x18); /* M->H ucode addr low */
1876 sz = EE_READ(sc, 0x1c); /* M->H ucode size */
1877 sz *= 4;
1878 addr = ((uint64_t)up << 32) | lo;
1879 injectucode(sc, UCODE_M2H, (bus_addr_t)addr, (bus_size_t)sz);
1880 #if UCODE_DEBUG == 1
1881 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz);
1882 #endif
1883
1884 lo = EE_READ(sc, 0x20); /* PKT ucode addr */
1885 sz = EE_READ(sc, 0x24); /* PKT ucode size */
1886 sz *= 4;
1887 injectucode(sc, UCODE_PKT, (bus_addr_t)lo, (bus_size_t)sz);
1888 #if UCODE_DEBUG == 1
1889 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz);
1890 #endif
1891 }
1892
1893 static void
injectucode(struct scx_softc * sc,int port,bus_addr_t addr,bus_size_t size)1894 injectucode(struct scx_softc *sc, int port,
1895 bus_addr_t addr, bus_size_t size)
1896 {
1897 bus_space_handle_t bsh;
1898 bus_size_t off;
1899 uint32_t ucode;
1900
1901 if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) {
1902 aprint_error_dev(sc->sc_dev,
1903 "eeprom map failure for ucode port 0x%x\n", port);
1904 return;
1905 }
1906 for (off = 0; off < size; off += 4) {
1907 ucode = bus_space_read_4(sc->sc_st, bsh, off);
1908 CSR_WRITE(sc, port, ucode);
1909 }
1910 bus_space_unmap(sc->sc_st, bsh, size);
1911 }
1912
1913 static void
forcephyloopback(struct scx_softc * sc)1914 forcephyloopback(struct scx_softc *sc)
1915 {
1916 struct device *d = sc->sc_dev;
1917 uint16_t val;
1918 int loop, err;
1919
1920 err = mii_readreg(d, sc->sc_phy_id, MII_BMCR, &val);
1921 if (err) {
1922 aprint_error_dev(d, "forcephyloopback() failed\n");
1923 return;
1924 }
1925 if (val & BMCR_PDOWN)
1926 val &= ~BMCR_PDOWN;
1927 val |= BMCR_ISO;
1928 (void)mii_writereg(d, sc->sc_phy_id, MII_BMCR, val);
1929 loop = 100;
1930 do {
1931 (void)mii_readreg(d, sc->sc_phy_id, MII_BMCR, &val);
1932 } while (loop-- > 0 && (val & (BMCR_PDOWN | BMCR_ISO)) != 0);
1933 (void)mii_writereg(d, sc->sc_phy_id, MII_BMCR, val | BMCR_LOOP);
1934 loop = 100;
1935 do {
1936 (void)mii_readreg(d, sc->sc_phy_id, MII_BMSR, &val);
1937 } while (loop-- > 0 && (val & BMSR_LINK) != 0);
1938 }
1939
1940 static void
resetphytonormal(struct scx_softc * sc)1941 resetphytonormal(struct scx_softc *sc)
1942 {
1943 struct device *d = sc->sc_dev;
1944 uint16_t val;
1945 int loop, err;
1946
1947 err = mii_readreg(d, sc->sc_phy_id, MII_BMCR, &val);
1948 if (err) {
1949 aprint_error_dev(d, "resetphytonormal() failed\n");
1950 }
1951 val &= ~BMCR_LOOP;
1952 (void)mii_writereg(d, sc->sc_phy_id, MII_BMCR, val);
1953 loop = 100;
1954 do {
1955 (void)mii_readreg(d, sc->sc_phy_id, MII_BMCR, &val);
1956 } while (loop-- > 0 && (val & BMCR_LOOP) != 0);
1957 (void)mii_writereg(d, sc->sc_phy_id, MII_BMCR, val | BMCR_RESET);
1958 loop = 100;
1959 do {
1960 (void)mii_readreg(d, sc->sc_phy_id, MII_BMCR, &val);
1961 } while (loop-- > 0 && (val & BMCR_RESET) != 0);
1962 }
1963
1964 /* GAR 5:2 MDIO frequency selection */
1965 static int
get_mdioclk(uint32_t freq)1966 get_mdioclk(uint32_t freq)
1967 {
1968
1969 freq /= 1000 * 1000;
1970 if (freq < 35)
1971 return GAR_MDIO_25_35MHZ;
1972 if (freq < 60)
1973 return GAR_MDIO_35_60MHZ;
1974 if (freq < 100)
1975 return GAR_MDIO_60_100MHZ;
1976 if (freq < 150)
1977 return GAR_MDIO_100_150MHZ;
1978 if (freq < 250)
1979 return GAR_MDIO_150_250MHZ;
1980 return GAR_MDIO_250_300MHZ;
1981 }
1982
1983 #define HWFEA_DEBUG 1
1984
1985 static void
dump_hwfeature(struct scx_softc * sc)1986 dump_hwfeature(struct scx_softc *sc)
1987 {
1988 #if HWFEA_DEBUG == 1
1989 struct {
1990 uint32_t bit;
1991 const char *des;
1992 } field[] = {
1993 { 27, "SA/VLAN insertion replacement enabled" },
1994 { 26, "flexible PPS enabled" },
1995 { 25, "time stamping with internal system enabled" },
1996 { 24, "alternate/enhanced descriptor enabled" },
1997 { 19, "rx FIFO >2048 enabled" },
1998 { 18, "type 2 IP checksum offload enabled" },
1999 { 17, "type 1 IP checksum offload enabled" },
2000 { 16, "Tx checksum offload enabled" },
2001 { 15, "AV feature enabled" },
2002 { 14, "EEE energy save feature enabled" },
2003 { 13, "1588-2008 version 2 advanced feature enabled" },
2004 { 12, "only 1588-2002 version 1 feature enabled" },
2005 { 11, "RMON event counter enabled" },
2006 { 10, "PMT magic packet enabled" },
2007 { 9, "PMT remote wakeup enabled" },
2008 { 8, "MDIO enabled", },
2009 { 7, "L3/L4 filter enabled" },
2010 { 6, "TBI/SGMII/RTBI support enabled" },
2011 { 5, "supplimental MAC address enabled" },
2012 { 4, "receive hash filter enabled" },
2013 { 3, "hash size is expanded" },
2014 { 2, "Half Duplex enabled" },
2015 { 1, "1000 Mbps enabled" },
2016 { 0, "10/100 Mbps enabled" },
2017 };
2018 const char *nameofmii[] = {
2019 "GMII or MII",
2020 "RGMII",
2021 "SGMII",
2022 "TBI",
2023 "RMII",
2024 "RTBI",
2025 "SMII",
2026 "RevMII"
2027 };
2028 uint32_t hwfea, mtype, txchan, rxchan;
2029
2030 hwfea = CSR_READ(sc, HWFEA);
2031 mtype = (hwfea & __BITS(30,28)) >> 28;
2032 aprint_normal("HWFEA 0x%08x\n", hwfea);
2033 aprint_normal("%s <30:28>\n", nameofmii[mtype]);
2034 for (unsigned i = 0; i < __arraycount(field); i++) {
2035 if ((hwfea & (1U << field[i].bit)) == 0)
2036 continue;
2037 aprint_normal("%s <%d>\n", field[i].des, field[i].bit);
2038 }
2039 if ((txchan = (hwfea & __BITS(23,22)) >> 22) != 0)
2040 aprint_normal("+%d tx channel available <23,22>\n", txchan);
2041 if ((rxchan = (hwfea & __BITS(21,20)) >> 20) != 0)
2042 aprint_normal("+%d rx channel available <21:20>\n", rxchan);
2043 return;
2044 #endif
2045 }
2046