1 /* $NetBSD: mvsocreg.h,v 1.14 2025/01/07 18:27:26 andvar Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _MVSOCREG_H_ 29 #define _MVSOCREG_H_ 30 31 #define MVSOC_UNITID_MASK 0xf 32 #define MVSOC_UNITID_DDR 0x0 /* DDR registers */ 33 #define MVSOC_UNITID_DEVBUS 0x1 /* Device Bus registers */ 34 #define MVSOC_UNITID_MLMB 0x2 /* Mbus-L to Mbus Bridge reg */ 35 #define MVSOC_UNITID_PEX 0x4 /* PCI Express Interface reg */ 36 37 38 #define MVSOC_INTERREGS_SIZE 0x00100000 /* 1 MB */ 39 40 41 /* 42 * Physical address of integrated peripherals 43 */ 44 45 #define UNITID2PHYS(uid) ((MVSOC_UNITID_ ## uid) << 16) 46 47 /* 48 * DDR SDRAM Controller Registers 49 */ 50 #define MVSOC_DDR_BASE (UNITID2PHYS(DDR)) /* 0x00000 */ 51 52 /* DDR SDRAM Controller Address Decode Registers */ 53 #define MVSOC_DSC_BASE 0x01500 /* DDR SDRAM Ctrl Addr Reg */ 54 #define MVSOC_DSC_NCS 4 55 #define MVSOC_DSC_CSBAR(x) ((x) * 8) 56 #define MVSOC_DSC_CSBAR_BASE_MASK 0xff000000 57 #define MVSOC_DSC_CSSR(x) ((x) * 8 + 4) 58 #define MVSOC_DSC_CSSR_WINEN 0x00000001 59 #define MVSOC_DSC_CSSR_SIZE_MASK 0xff000000 60 61 /* 62 * Device Bus 63 */ 64 #define MVSOC_DEVBUS_BASE (UNITID2PHYS(DEVBUS)) /* 0x10000 */ 65 66 /* 67 * General Purpose Port Registers 68 */ 69 #define MVSOC_GPP_BASE (MVSOC_DEVBUS_BASE + 0x0100) 70 71 /* 72 * Two-Wire Serial Interface Registers 73 */ 74 #define MVSOC_TWSI_BASE (MVSOC_DEVBUS_BASE + 0x1000) 75 76 /* 77 * UART Interface Registers 78 */ 79 /* NS16550 compatible */ 80 #define MVSOC_COM0_BASE (MVSOC_DEVBUS_BASE + 0x2000) 81 #define MVSOC_COM1_BASE (MVSOC_DEVBUS_BASE + 0x2100) 82 83 /* 84 * Mbus-L to Mbus Bridge Registers 85 */ 86 #define MVSOC_MLMB_BASE (UNITID2PHYS(MLMB)) /* 0x20000 */ 87 88 /* CPU Address Map Registers */ 89 #define MVSOC_MLMB_WCR(w) ((w) < 8 ? ((w) << 4) + 0x0 :\ 90 (((w) - 8) << 3) + 0x90) 91 #define MVSOC_MLMB_WCR_WINEN (1 << 0) 92 #define MVSOC_MLMB_WCR_SYNC (1 << 1) /* sync barrier */ 93 #define MVSOC_MLMB_WCR_TARGET(t) (((t) & 0xf) << 4) 94 #define MVSOC_MLMB_WCR_GET_TARGET(reg) (((reg) >> 4) & 0xf) 95 #define MVSOC_MLMB_WCR_ATTR(a) (((a) & 0xff) << 8) 96 #define MVSOC_MLMB_WCR_GET_ATTR(reg) (((reg) >> 8) & 0xff) 97 #define MVSOC_MLMB_WCR_SIZE_MASK 0xffff0000 98 #define MVSOC_MLMB_WCR_SIZE(s) (((s) - 1) & MVSOC_MLMB_WCR_SIZE_MASK) 99 #define MVSOC_MLMB_WCR_GET_SIZE(reg) \ 100 (((reg) & MVSOC_MLMB_WCR_SIZE_MASK) + (1 << 16)) 101 #define MVSOC_MLMB_WBR(w) ((w) < 8 ? ((w) << 4) + 0x4 :\ 102 (((w) - 8) << 3) + 0x94) 103 #define MVSOC_MLMB_WBR_BASE_MASK 0xffff0000 104 #define MVSOC_MLMB_WBR_GET_BASE(reg) (reg & MVSOC_MLMB_WBR_BASE_MASK) 105 #define MVSOC_MLMB_WRLR(w) (((w) << 4) + 0x8) 106 #define MVSOC_MLMB_WRLR_REMAP_MASK 0xffff0000 107 #define MVSOC_MLMB_WRLR_GET_REMAP(reg) \ 108 (reg & MVSOC_MLMB_WRLR_REMAP_MASK) 109 #define MVSOC_MLMB_WRHR(w) (((w) << 4) + 0xc) 110 #define MVSOC_MLMB_IRBAR 0x080 /* Internal regs Base Address */ 111 #define MVSOC_MLMB_IRBAR_BASE_MASK 0xfff00000 112 113 /* CPU Control and Status Registers */ 114 #define MVSOC_MLMB_CPUCR 0x100 /* CPU Configuration Register */ 115 #define MVSOC_MLMB_CPUCSR 0x104 /* CPU Control/Status Register*/ 116 #define MVSOC_MLMB_RSTOUTNMASKR 0x108 /* RSTOUTn Mask Register */ 117 #define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN (1 << 2) 118 #define MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN (1 << 1) 119 #define MVSOC_MLMB_RSTOUTNMASKR_PEXRSTOUTEN (1 << 0) 120 #define MVSOC_MLMB_SSRR 0x10c /* System Soft Reset Register */ 121 #define MVSOC_MLMB_SSRR_SYSTEMSOFTRST (1 << 0) 122 #define MVSOC_MLMB_MLMBICR 0x110 /*Mb-L to Mb Bridge Intr Cause*/ 123 #define MVSOC_MLMB_MLMBIMR 0x114 /*Mb-L to Mb Bridge Intr Mask */ 124 125 #define MVSOC_MLMB_CLKGATING 0x11c /* Clock Gating Control */ 126 #define MVSOC_MLMB_CLKGATING_LNR (1 << 13) /* Load New Ratio */ 127 #define MVSOC_MLMB_CLKGATING_GPH (1 << 12) /* Go To Power Half */ 128 #define MVSOC_MLMB_CLKGATING_GPS (1 << 11) /* Go To Power Save */ 129 #define MVSOC_MLMB_CLKGATING_CR (1 << 10) /* Production Realignment */ 130 #define MVSOC_MLMB_CLKGATING_BIT(n) (1 << (n)) 131 132 #define MVSOC_MLMB_L2CFG 0x128 /* L2 Cache Config */ 133 134 #define MVSOC_MLMB_NWIN 4 135 #define MVSOC_MLMB_WINBAR(w) (((w) << 3) + 0x180) 136 #define MVSOC_MLMB_WINBAR_BASE_MASK 0xff000000 137 #define MVSOC_MLMB_WINCR(w) (((w) << 3) + 0x184) 138 #define MVSOC_MLMB_WINCR_EN (1 << 0) 139 #define MVSOC_MLMB_WINCR_WINCS(x) (((x) & 0x1c) >> 2) 140 #define MVSOC_MLMB_WINCR_SIZE_MASK 0xff000000 141 142 /* Coherent Fabric(CFU) Control and Status */ 143 #define MVSOC_MLMB_CFU_FAB_CTRL 0x200 144 #define MVSOC_MLMB_CFU_FAB_CTRL_PROP_ERR (0x1 << 8) 145 #define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU0 (0x1 << 24) 146 #define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU1 (0x1 << 25) 147 #define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU2 (0x1 << 26) 148 #define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU3 (0x1 << 27) 149 150 /* Coherent Fabiric Configuration */ 151 #define MVSOC_MLMB_CFU_FAB_CFG 0x204 152 153 /* CFU IO Event Affinity */ 154 #define MVSOC_MLMB_CFU_EVA 0x208 155 156 /* CFU IO Snoop Affinity */ 157 #define MVSOC_MLMB_CFU_IOA 0x20c 158 159 /* CFU Configuration XXX: changed in ARMADA 370 */ 160 #define MVSOC_MLMB_CFU_CFG 0x228 161 #define MVSOC_MLMB_CFU_CFG_L2_NOTIFY (0x1 << 16) 162 163 /* CIB registers offsets */ 164 #define MVSOC_MLMB_CIB_CTRL_CFG 0x280 165 #define MVSOC_MLMB_CIB_CTRL_CFG_WB_EN (0x1 << 0) 166 #define MVSOC_MLMB_CIB_CTRL_CFG_STOP (0x1 << 9) 167 #define MVSOC_MLMB_CIB_CTRL_CFG_IGN_SHARE (0x2 << 10) 168 #define MVSOC_MLMB_CIB_CTRL_CFG_EMPTY (0x1 << 13) 169 170 /* CIB barrier register */ 171 #define MVSOC_MLMB_CIB_BARRIER(cpu) (0x1810 + 0x100 * (cpu)) 172 #define MVSOC_MLMB_CIB_BARRIER_TRIGGER (0x1 << 0) 173 174 #define MVSOC_TMR_BASE (MVSOC_MLMB_BASE + 0x0300) 175 176 /* CPU Doorbell Registers */ 177 #define MVSOC_MLMB_H2CDR 0x400 /* Host-to-CPU Doorbell */ 178 #define MVSOC_MLMB_H2CDMR 0x404 /* Host-to-CPU Doorbell Mask */ 179 #define MVSOC_MLMB_C2HDR 0x408 /* CPU-to-Host Doorbell */ 180 #define MVSOC_MLMB_C2HDMR 0x40c /* CPU-to-Host Doorbell Mask */ 181 182 /* Local to System Bridge Interrupt {Cause,Mask} Register bits */ 183 #define MVSOC_MLMB_MLMBI_CPUSELFINT 0 184 #define MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ 1 185 #define MVSOC_MLMB_MLMBI_CPUTIMER1INTREQ 2 186 #define MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ 3 187 #define MVSOC_MLMB_MLMBI_ACCESSERR 4 188 #define MVSOC_MLMB_MLMBI_BIT64ERR 5 189 #define MVSOC_MLMB_MLMBI_CPUTIMER2INTREQ 6 190 #define MVSOC_MLMB_MLMBI_CPUTIMER3INTREQ 7 191 192 #define MVSOC_MLMB_MLMBI_NIRQ 8 193 194 /* 195 * PCI-Express Interface Registers 196 */ 197 #define MVSOC_PEX_BASE (UNITID2PHYS(PEX)) /* 0x40000 */ 198 199 200 /* 201 * AXI's DDR Controller Registers 202 * used by Dove only ??? 203 */ 204 205 /* DDR SDRAM Controller Address Decode Registers */ 206 #define MVSOC_AXI_NCS 2 207 #define MVSOC_AXI_MMAP1(cs) (((cs) << 4) + 0x100) 208 #define MVSOC_AXI_MMAP1_STARTADDRESS(v) ((v) & 0xff800000) 209 #define MVSOC_AXI_MMAP1_AREALENGTH(v) (0x10000 << (((v) & 0xf0000) >> 16)) 210 #define MVSOC_AXI_MMAP1_ADDRESSMASK (0x1ff << 7) 211 #define MVSOC_AXI_MMAP1_VALID (1 << 0) 212 213 #endif /* _MVSOCREG_H_ */ 214