1 /* $OpenBSD: pte.h,v 1.24 2023/01/11 03:17:56 visa Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and Ralph Campbell. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah Hdr: pte.h 1.11 89/09/03 37 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93 38 */ 39 40 /* 41 * R4000 and R8000 hardware page table entries 42 */ 43 44 #ifndef _MIPS64_PTE_H_ 45 #define _MIPS64_PTE_H_ 46 47 #ifndef _LOCORE 48 49 /* 50 * Structure defining a TLB entry data set. 51 */ 52 struct tlb_entry { 53 u_int64_t tlb_mask; 54 u_int64_t tlb_hi; 55 u_int64_t tlb_lo0; 56 u_int64_t tlb_lo1; 57 }; 58 59 u_int tlb_get_pid(void); 60 void tlb_read(unsigned int, struct tlb_entry *); 61 62 #ifdef MIPS_PTE64 63 typedef u_int64_t pt_entry_t; 64 #else 65 typedef u_int32_t pt_entry_t; 66 #endif 67 68 #endif /* _LOCORE */ 69 70 #ifdef MIPS_PTE64 71 #define PTE_BITS 64 72 #define PTE_LOAD ld 73 #define PTE_LOG 3 74 #define PTE_OFFS 8 75 #else 76 #define PTE_BITS 32 77 #define PTE_LOAD lwu 78 #define PTE_LOG 2 79 #define PTE_OFFS 4 80 #endif 81 82 #if defined(CPU_MIPS64R2) && !defined(CPU_LOONGSON2) 83 #define PTE_CLEAR_SWBITS(reg) \ 84 .set push; \ 85 .set mips64r2; \ 86 /* Clear SW bits between PG_XI and PG_FRAMEBITS. */ \ 87 dins reg, zero, PG_FRAMEBITS, (PTE_BITS - 2 - PG_FRAMEBITS); \ 88 .set pop 89 #else 90 #define PTE_CLEAR_SWBITS(reg) \ 91 /* Clear SW bits left of PG_FRAMEBITS. */ \ 92 dsll reg, reg, (64 - PG_FRAMEBITS); \ 93 dsrl reg, reg, (64 - PG_FRAMEBITS) 94 #endif 95 96 /* entryhi values */ 97 98 #define PG_HVPN (-2 * PAGE_SIZE) /* Hardware page number mask */ 99 #define PG_ODDPG PAGE_SIZE 100 101 /* Address space ID */ 102 #define PG_ASID_MASK 0x00000000000000ff 103 #define PG_ASID_SHIFT 0 104 #define MIN_USER_ASID 1 105 #define PG_ASID_COUNT 256 /* Number of available ASID */ 106 107 /* entrylo values */ 108 109 #ifdef MIPS_PTE64 110 #define PG_FRAMEBITS 60 111 #else 112 #define PG_FRAMEBITS 28 113 #endif 114 #define PG_FRAME ((1ULL << PG_FRAMEBITS) - (1ULL << PG_SHIFT)) 115 #define PG_SHIFT 6 116 117 /* software pte bits - not put in entrylo */ 118 #define PG_WIRED (1ULL << (PG_FRAMEBITS + 1)) 119 #define PG_RO (1ULL << (PG_FRAMEBITS + 0)) 120 121 #ifdef CPU_MIPS64R2 122 #define PG_RI (1ULL << (PG_FRAMEBITS + 3)) 123 #define PG_XI (1ULL << (PG_FRAMEBITS + 2)) 124 #else 125 #define PG_RI 0x00000000 126 #define PG_XI 0x00000000 127 #endif 128 129 #define PG_NV 0x00000000 130 #define PG_G 0x00000001 131 #define PG_V 0x00000002 132 #define PG_M 0x00000004 133 #define PG_CCA_SHIFT 3 134 135 #define PG_UNCACHED (CCA_NC << PG_CCA_SHIFT) 136 #define PG_CACHED_NC (CCA_NONCOHERENT << PG_CCA_SHIFT) 137 #define PG_CACHED_CE (CCA_COHERENT_EXCL << PG_CCA_SHIFT) 138 #define PG_CACHED_CEW (CCA_COHERENT_EXCLWRITE << PG_CCA_SHIFT) 139 #define PG_CACHED (CCA_CACHED << PG_CCA_SHIFT) 140 #define PG_CACHEMODE (7 << PG_CCA_SHIFT) 141 142 #define PG_PROTMASK (PG_M | PG_RO | PG_RI | PG_XI) 143 144 #define pfn_to_pad(pa) ((((paddr_t)pa) & PG_FRAME) << PG_SHIFT) 145 #define vad_to_pfn(va) (((va) >> PG_SHIFT) & PG_FRAME) 146 147 #define PG_SIZE_4K 0x00000000 148 #define PG_SIZE_16K 0x00006000 149 #define PG_SIZE_64K 0x0001e000 150 #define PG_SIZE_256K 0x0007e000 151 #define PG_SIZE_1M 0x001fe000 152 #define PG_SIZE_4M 0x007fe000 153 #define PG_SIZE_16M 0x01ffe000 154 #if PAGE_SHIFT == 12 155 #define TLB_PAGE_MASK PG_SIZE_4K 156 #elif PAGE_SHIFT == 14 157 #define TLB_PAGE_MASK PG_SIZE_16K 158 #endif 159 160 #endif /* !_MIPS64_PTE_H_ */ 161