1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the AArch64 target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 17 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 18 19 // FIXME: Is it easiest to fix this layering violation by moving the .inc 20 // #includes from AArch64MCTargetDesc.h to here? 21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends. 22 #include "llvm/ADT/BitmaskEnum.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringSwitch.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/TargetParser/SubtargetFeature.h" 27 28 namespace llvm { 29 30 inline static MCRegister getWRegFromXReg(MCRegister Reg) { 31 switch (Reg.id()) { 32 case AArch64::X0: return AArch64::W0; 33 case AArch64::X1: return AArch64::W1; 34 case AArch64::X2: return AArch64::W2; 35 case AArch64::X3: return AArch64::W3; 36 case AArch64::X4: return AArch64::W4; 37 case AArch64::X5: return AArch64::W5; 38 case AArch64::X6: return AArch64::W6; 39 case AArch64::X7: return AArch64::W7; 40 case AArch64::X8: return AArch64::W8; 41 case AArch64::X9: return AArch64::W9; 42 case AArch64::X10: return AArch64::W10; 43 case AArch64::X11: return AArch64::W11; 44 case AArch64::X12: return AArch64::W12; 45 case AArch64::X13: return AArch64::W13; 46 case AArch64::X14: return AArch64::W14; 47 case AArch64::X15: return AArch64::W15; 48 case AArch64::X16: return AArch64::W16; 49 case AArch64::X17: return AArch64::W17; 50 case AArch64::X18: return AArch64::W18; 51 case AArch64::X19: return AArch64::W19; 52 case AArch64::X20: return AArch64::W20; 53 case AArch64::X21: return AArch64::W21; 54 case AArch64::X22: return AArch64::W22; 55 case AArch64::X23: return AArch64::W23; 56 case AArch64::X24: return AArch64::W24; 57 case AArch64::X25: return AArch64::W25; 58 case AArch64::X26: return AArch64::W26; 59 case AArch64::X27: return AArch64::W27; 60 case AArch64::X28: return AArch64::W28; 61 case AArch64::FP: return AArch64::W29; 62 case AArch64::LR: return AArch64::W30; 63 case AArch64::SP: return AArch64::WSP; 64 case AArch64::XZR: return AArch64::WZR; 65 } 66 // For anything else, return it unchanged. 67 return Reg; 68 } 69 70 inline static MCRegister getXRegFromWReg(MCRegister Reg) { 71 switch (Reg.id()) { 72 case AArch64::W0: return AArch64::X0; 73 case AArch64::W1: return AArch64::X1; 74 case AArch64::W2: return AArch64::X2; 75 case AArch64::W3: return AArch64::X3; 76 case AArch64::W4: return AArch64::X4; 77 case AArch64::W5: return AArch64::X5; 78 case AArch64::W6: return AArch64::X6; 79 case AArch64::W7: return AArch64::X7; 80 case AArch64::W8: return AArch64::X8; 81 case AArch64::W9: return AArch64::X9; 82 case AArch64::W10: return AArch64::X10; 83 case AArch64::W11: return AArch64::X11; 84 case AArch64::W12: return AArch64::X12; 85 case AArch64::W13: return AArch64::X13; 86 case AArch64::W14: return AArch64::X14; 87 case AArch64::W15: return AArch64::X15; 88 case AArch64::W16: return AArch64::X16; 89 case AArch64::W17: return AArch64::X17; 90 case AArch64::W18: return AArch64::X18; 91 case AArch64::W19: return AArch64::X19; 92 case AArch64::W20: return AArch64::X20; 93 case AArch64::W21: return AArch64::X21; 94 case AArch64::W22: return AArch64::X22; 95 case AArch64::W23: return AArch64::X23; 96 case AArch64::W24: return AArch64::X24; 97 case AArch64::W25: return AArch64::X25; 98 case AArch64::W26: return AArch64::X26; 99 case AArch64::W27: return AArch64::X27; 100 case AArch64::W28: return AArch64::X28; 101 case AArch64::W29: return AArch64::FP; 102 case AArch64::W30: return AArch64::LR; 103 case AArch64::WSP: return AArch64::SP; 104 case AArch64::WZR: return AArch64::XZR; 105 } 106 // For anything else, return it unchanged. 107 return Reg; 108 } 109 110 inline static MCRegister getXRegFromXRegTuple(MCRegister RegTuple) { 111 switch (RegTuple.id()) { 112 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0; 113 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2; 114 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4; 115 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13: return AArch64::X6; 116 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15: return AArch64::X8; 117 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17: return AArch64::X10; 118 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19: return AArch64::X12; 119 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21: return AArch64::X14; 120 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16; 121 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25: return AArch64::X18; 122 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27: return AArch64::X20; 123 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP: return AArch64::X22; 124 } 125 // For anything else, return it unchanged. 126 return RegTuple; 127 } 128 129 static inline MCRegister getBRegFromDReg(MCRegister Reg) { 130 switch (Reg.id()) { 131 case AArch64::D0: return AArch64::B0; 132 case AArch64::D1: return AArch64::B1; 133 case AArch64::D2: return AArch64::B2; 134 case AArch64::D3: return AArch64::B3; 135 case AArch64::D4: return AArch64::B4; 136 case AArch64::D5: return AArch64::B5; 137 case AArch64::D6: return AArch64::B6; 138 case AArch64::D7: return AArch64::B7; 139 case AArch64::D8: return AArch64::B8; 140 case AArch64::D9: return AArch64::B9; 141 case AArch64::D10: return AArch64::B10; 142 case AArch64::D11: return AArch64::B11; 143 case AArch64::D12: return AArch64::B12; 144 case AArch64::D13: return AArch64::B13; 145 case AArch64::D14: return AArch64::B14; 146 case AArch64::D15: return AArch64::B15; 147 case AArch64::D16: return AArch64::B16; 148 case AArch64::D17: return AArch64::B17; 149 case AArch64::D18: return AArch64::B18; 150 case AArch64::D19: return AArch64::B19; 151 case AArch64::D20: return AArch64::B20; 152 case AArch64::D21: return AArch64::B21; 153 case AArch64::D22: return AArch64::B22; 154 case AArch64::D23: return AArch64::B23; 155 case AArch64::D24: return AArch64::B24; 156 case AArch64::D25: return AArch64::B25; 157 case AArch64::D26: return AArch64::B26; 158 case AArch64::D27: return AArch64::B27; 159 case AArch64::D28: return AArch64::B28; 160 case AArch64::D29: return AArch64::B29; 161 case AArch64::D30: return AArch64::B30; 162 case AArch64::D31: return AArch64::B31; 163 } 164 // For anything else, return it unchanged. 165 return Reg; 166 } 167 168 static inline MCRegister getDRegFromBReg(MCRegister Reg) { 169 switch (Reg.id()) { 170 case AArch64::B0: return AArch64::D0; 171 case AArch64::B1: return AArch64::D1; 172 case AArch64::B2: return AArch64::D2; 173 case AArch64::B3: return AArch64::D3; 174 case AArch64::B4: return AArch64::D4; 175 case AArch64::B5: return AArch64::D5; 176 case AArch64::B6: return AArch64::D6; 177 case AArch64::B7: return AArch64::D7; 178 case AArch64::B8: return AArch64::D8; 179 case AArch64::B9: return AArch64::D9; 180 case AArch64::B10: return AArch64::D10; 181 case AArch64::B11: return AArch64::D11; 182 case AArch64::B12: return AArch64::D12; 183 case AArch64::B13: return AArch64::D13; 184 case AArch64::B14: return AArch64::D14; 185 case AArch64::B15: return AArch64::D15; 186 case AArch64::B16: return AArch64::D16; 187 case AArch64::B17: return AArch64::D17; 188 case AArch64::B18: return AArch64::D18; 189 case AArch64::B19: return AArch64::D19; 190 case AArch64::B20: return AArch64::D20; 191 case AArch64::B21: return AArch64::D21; 192 case AArch64::B22: return AArch64::D22; 193 case AArch64::B23: return AArch64::D23; 194 case AArch64::B24: return AArch64::D24; 195 case AArch64::B25: return AArch64::D25; 196 case AArch64::B26: return AArch64::D26; 197 case AArch64::B27: return AArch64::D27; 198 case AArch64::B28: return AArch64::D28; 199 case AArch64::B29: return AArch64::D29; 200 case AArch64::B30: return AArch64::D30; 201 case AArch64::B31: return AArch64::D31; 202 } 203 // For anything else, return it unchanged. 204 return Reg; 205 } 206 207 static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) { 208 switch (Opcode) { 209 case AArch64::LDADDAB: case AArch64::LDADDAH: 210 case AArch64::LDADDAW: case AArch64::LDADDAX: 211 case AArch64::LDADDALB: case AArch64::LDADDALH: 212 case AArch64::LDADDALW: case AArch64::LDADDALX: 213 case AArch64::LDCLRAB: case AArch64::LDCLRAH: 214 case AArch64::LDCLRAW: case AArch64::LDCLRAX: 215 case AArch64::LDCLRALB: case AArch64::LDCLRALH: 216 case AArch64::LDCLRALW: case AArch64::LDCLRALX: 217 case AArch64::LDEORAB: case AArch64::LDEORAH: 218 case AArch64::LDEORAW: case AArch64::LDEORAX: 219 case AArch64::LDEORALB: case AArch64::LDEORALH: 220 case AArch64::LDEORALW: case AArch64::LDEORALX: 221 case AArch64::LDSETAB: case AArch64::LDSETAH: 222 case AArch64::LDSETAW: case AArch64::LDSETAX: 223 case AArch64::LDSETALB: case AArch64::LDSETALH: 224 case AArch64::LDSETALW: case AArch64::LDSETALX: 225 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH: 226 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX: 227 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH: 228 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX: 229 case AArch64::LDSMINAB: case AArch64::LDSMINAH: 230 case AArch64::LDSMINAW: case AArch64::LDSMINAX: 231 case AArch64::LDSMINALB: case AArch64::LDSMINALH: 232 case AArch64::LDSMINALW: case AArch64::LDSMINALX: 233 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH: 234 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX: 235 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH: 236 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX: 237 case AArch64::LDUMINAB: case AArch64::LDUMINAH: 238 case AArch64::LDUMINAW: case AArch64::LDUMINAX: 239 case AArch64::LDUMINALB: case AArch64::LDUMINALH: 240 case AArch64::LDUMINALW: case AArch64::LDUMINALX: 241 case AArch64::SWPAB: case AArch64::SWPAH: 242 case AArch64::SWPAW: case AArch64::SWPAX: 243 case AArch64::SWPALB: case AArch64::SWPALH: 244 case AArch64::SWPALW: case AArch64::SWPALX: 245 return true; 246 } 247 return false; 248 } 249 250 namespace AArch64CC { 251 252 // The CondCodes constants map directly to the 4-bit encoding of the condition 253 // field for predicated instructions. 254 enum CondCode { // Meaning (integer) Meaning (floating-point) 255 EQ = 0x0, // Equal Equal 256 NE = 0x1, // Not equal Not equal, or unordered 257 HS = 0x2, // Unsigned higher or same >, ==, or unordered 258 LO = 0x3, // Unsigned lower Less than 259 MI = 0x4, // Minus, negative Less than 260 PL = 0x5, // Plus, positive or zero >, ==, or unordered 261 VS = 0x6, // Overflow Unordered 262 VC = 0x7, // No overflow Not unordered 263 HI = 0x8, // Unsigned higher Greater than, or unordered 264 LS = 0x9, // Unsigned lower or same Less than or equal 265 GE = 0xa, // Greater than or equal Greater than or equal 266 LT = 0xb, // Less than Less than, or unordered 267 GT = 0xc, // Greater than Greater than 268 LE = 0xd, // Less than or equal <, ==, or unordered 269 AL = 0xe, // Always (unconditional) Always (unconditional) 270 NV = 0xf, // Always (unconditional) Always (unconditional) 271 // Note the NV exists purely to disassemble 0b1111. Execution is "always". 272 Invalid, 273 274 // Common aliases used for SVE. 275 ANY_ACTIVE = NE, // (!Z) 276 FIRST_ACTIVE = MI, // ( N) 277 LAST_ACTIVE = LO, // (!C) 278 NONE_ACTIVE = EQ // ( Z) 279 }; 280 281 inline static const char *getCondCodeName(CondCode Code) { 282 switch (Code) { 283 default: llvm_unreachable("Unknown condition code"); 284 case EQ: return "eq"; 285 case NE: return "ne"; 286 case HS: return "hs"; 287 case LO: return "lo"; 288 case MI: return "mi"; 289 case PL: return "pl"; 290 case VS: return "vs"; 291 case VC: return "vc"; 292 case HI: return "hi"; 293 case LS: return "ls"; 294 case GE: return "ge"; 295 case LT: return "lt"; 296 case GT: return "gt"; 297 case LE: return "le"; 298 case AL: return "al"; 299 case NV: return "nv"; 300 } 301 } 302 303 inline static CondCode getInvertedCondCode(CondCode Code) { 304 // To reverse a condition it's necessary to only invert the low bit: 305 306 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 307 } 308 309 /// getSwappedCondition - assume the flags are set by MI(a,b), return 310 /// the condition code if we modify the instructions such that flags are 311 /// set by MI(b,a). 312 inline static CondCode getSwappedCondition(CondCode CC) { 313 switch (CC) { 314 default: 315 return AL; 316 case EQ: 317 return EQ; 318 case NE: 319 return NE; 320 case HS: 321 return LS; 322 case LO: 323 return HI; 324 case HI: 325 return LO; 326 case LS: 327 return HS; 328 case GE: 329 return LE; 330 case LT: 331 return GT; 332 case GT: 333 return LT; 334 case LE: 335 return GE; 336 } 337 } 338 339 /// Given a condition code, return NZCV flags that would satisfy that condition. 340 /// The flag bits are in the format expected by the ccmp instructions. 341 /// Note that many different flag settings can satisfy a given condition code, 342 /// this function just returns one of them. 343 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { 344 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. 345 enum { N = 8, Z = 4, C = 2, V = 1 }; 346 switch (Code) { 347 default: llvm_unreachable("Unknown condition code"); 348 case EQ: return Z; // Z == 1 349 case NE: return 0; // Z == 0 350 case HS: return C; // C == 1 351 case LO: return 0; // C == 0 352 case MI: return N; // N == 1 353 case PL: return 0; // N == 0 354 case VS: return V; // V == 1 355 case VC: return 0; // V == 0 356 case HI: return C; // C == 1 && Z == 0 357 case LS: return 0; // C == 0 || Z == 1 358 case GE: return 0; // N == V 359 case LT: return N; // N != V 360 case GT: return 0; // Z == 0 && N == V 361 case LE: return Z; // Z == 1 || N != V 362 } 363 } 364 365 } // end namespace AArch64CC 366 367 struct SysAlias { 368 const char *Name; 369 uint16_t Encoding; 370 FeatureBitset FeaturesRequired; 371 372 constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {} 373 constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F) 374 : Name(N), Encoding(E), FeaturesRequired(F) {} 375 376 bool haveFeatures(FeatureBitset ActiveFeatures) const { 377 return ActiveFeatures[llvm::AArch64::FeatureAll] || 378 (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 379 } 380 381 FeatureBitset getRequiredFeatures() const { return FeaturesRequired; } 382 }; 383 384 struct SysAliasReg : SysAlias { 385 bool NeedsReg; 386 constexpr SysAliasReg(const char *N, uint16_t E, bool R) 387 : SysAlias(N, E), NeedsReg(R) {} 388 constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F) 389 : SysAlias(N, E, F), NeedsReg(R) {} 390 }; 391 392 struct SysAliasImm : SysAlias { 393 uint16_t ImmValue; 394 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I) 395 : SysAlias(N, E), ImmValue(I) {} 396 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F) 397 : SysAlias(N, E, F), ImmValue(I) {} 398 }; 399 400 namespace AArch64SVCR { 401 struct SVCR : SysAlias{ 402 using SysAlias::SysAlias; 403 }; 404 #define GET_SVCRValues_DECL 405 #define GET_SVCRsList_DECL 406 #include "AArch64GenSystemOperands.inc" 407 } 408 409 namespace AArch64AT{ 410 struct AT : SysAlias { 411 using SysAlias::SysAlias; 412 }; 413 #define GET_ATValues_DECL 414 #define GET_ATsList_DECL 415 #include "AArch64GenSystemOperands.inc" 416 } 417 418 namespace AArch64DB { 419 struct DB : SysAlias { 420 using SysAlias::SysAlias; 421 }; 422 #define GET_DBValues_DECL 423 #define GET_DBsList_DECL 424 #include "AArch64GenSystemOperands.inc" 425 } 426 427 namespace AArch64DBnXS { 428 struct DBnXS : SysAliasImm { 429 using SysAliasImm::SysAliasImm; 430 }; 431 #define GET_DBnXSValues_DECL 432 #define GET_DBnXSsList_DECL 433 #include "AArch64GenSystemOperands.inc" 434 } 435 436 namespace AArch64DC { 437 struct DC : SysAlias { 438 using SysAlias::SysAlias; 439 }; 440 #define GET_DCValues_DECL 441 #define GET_DCsList_DECL 442 #include "AArch64GenSystemOperands.inc" 443 } 444 445 namespace AArch64IC { 446 struct IC : SysAliasReg { 447 using SysAliasReg::SysAliasReg; 448 }; 449 #define GET_ICValues_DECL 450 #define GET_ICsList_DECL 451 #include "AArch64GenSystemOperands.inc" 452 } 453 454 namespace AArch64ISB { 455 struct ISB : SysAlias { 456 using SysAlias::SysAlias; 457 }; 458 #define GET_ISBValues_DECL 459 #define GET_ISBsList_DECL 460 #include "AArch64GenSystemOperands.inc" 461 } 462 463 namespace AArch64TSB { 464 struct TSB : SysAlias { 465 using SysAlias::SysAlias; 466 }; 467 #define GET_TSBValues_DECL 468 #define GET_TSBsList_DECL 469 #include "AArch64GenSystemOperands.inc" 470 } 471 472 namespace AArch64PRFM { 473 struct PRFM : SysAlias { 474 using SysAlias::SysAlias; 475 }; 476 #define GET_PRFMValues_DECL 477 #define GET_PRFMsList_DECL 478 #include "AArch64GenSystemOperands.inc" 479 } 480 481 namespace AArch64SVEPRFM { 482 struct SVEPRFM : SysAlias { 483 using SysAlias::SysAlias; 484 }; 485 #define GET_SVEPRFMValues_DECL 486 #define GET_SVEPRFMsList_DECL 487 #include "AArch64GenSystemOperands.inc" 488 } 489 490 namespace AArch64RPRFM { 491 struct RPRFM : SysAlias { 492 using SysAlias::SysAlias; 493 }; 494 #define GET_RPRFMValues_DECL 495 #define GET_RPRFMsList_DECL 496 #include "AArch64GenSystemOperands.inc" 497 } // namespace AArch64RPRFM 498 499 namespace AArch64SVEPredPattern { 500 struct SVEPREDPAT { 501 const char *Name; 502 uint16_t Encoding; 503 }; 504 #define GET_SVEPREDPATValues_DECL 505 #define GET_SVEPREDPATsList_DECL 506 #include "AArch64GenSystemOperands.inc" 507 } 508 509 namespace AArch64SVEVecLenSpecifier { 510 struct SVEVECLENSPECIFIER { 511 const char *Name; 512 uint16_t Encoding; 513 }; 514 #define GET_SVEVECLENSPECIFIERValues_DECL 515 #define GET_SVEVECLENSPECIFIERsList_DECL 516 #include "AArch64GenSystemOperands.inc" 517 } // namespace AArch64SVEVecLenSpecifier 518 519 /// Return the number of active elements for VL1 to VL256 predicate pattern, 520 /// zero for all other patterns. 521 inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) { 522 switch (Pattern) { 523 default: 524 return 0; 525 case AArch64SVEPredPattern::vl1: 526 case AArch64SVEPredPattern::vl2: 527 case AArch64SVEPredPattern::vl3: 528 case AArch64SVEPredPattern::vl4: 529 case AArch64SVEPredPattern::vl5: 530 case AArch64SVEPredPattern::vl6: 531 case AArch64SVEPredPattern::vl7: 532 case AArch64SVEPredPattern::vl8: 533 return Pattern; 534 case AArch64SVEPredPattern::vl16: 535 return 16; 536 case AArch64SVEPredPattern::vl32: 537 return 32; 538 case AArch64SVEPredPattern::vl64: 539 return 64; 540 case AArch64SVEPredPattern::vl128: 541 return 128; 542 case AArch64SVEPredPattern::vl256: 543 return 256; 544 } 545 } 546 547 /// Return specific VL predicate pattern based on the number of elements. 548 inline std::optional<unsigned> 549 getSVEPredPatternFromNumElements(unsigned MinNumElts) { 550 switch (MinNumElts) { 551 default: 552 return std::nullopt; 553 case 1: 554 case 2: 555 case 3: 556 case 4: 557 case 5: 558 case 6: 559 case 7: 560 case 8: 561 return MinNumElts; 562 case 16: 563 return AArch64SVEPredPattern::vl16; 564 case 32: 565 return AArch64SVEPredPattern::vl32; 566 case 64: 567 return AArch64SVEPredPattern::vl64; 568 case 128: 569 return AArch64SVEPredPattern::vl128; 570 case 256: 571 return AArch64SVEPredPattern::vl256; 572 } 573 } 574 575 /// An enum to describe what types of loops we should attempt to tail-fold: 576 /// Disabled: None 577 /// Reductions: Loops containing reductions 578 /// Recurrences: Loops with first-order recurrences, i.e. that would 579 /// require a SVE splice instruction 580 /// Reverse: Reverse loops 581 /// Simple: Loops that are not reversed and don't contain reductions 582 /// or first-order recurrences. 583 /// All: All 584 enum class TailFoldingOpts : uint8_t { 585 Disabled = 0x00, 586 Simple = 0x01, 587 Reductions = 0x02, 588 Recurrences = 0x04, 589 Reverse = 0x08, 590 All = Reductions | Recurrences | Simple | Reverse 591 }; 592 593 LLVM_DECLARE_ENUM_AS_BITMASK(TailFoldingOpts, 594 /* LargestValue */ (long)TailFoldingOpts::Reverse); 595 596 namespace AArch64ExactFPImm { 597 struct ExactFPImm { 598 int Enum; 599 const char *Repr; 600 }; 601 #define GET_ExactFPImmValues_DECL 602 #define GET_ExactFPImmsList_DECL 603 #include "AArch64GenSystemOperands.inc" 604 } 605 606 namespace AArch64PState { 607 struct PStateImm0_15 : SysAlias{ 608 using SysAlias::SysAlias; 609 }; 610 #define GET_PStateImm0_15Values_DECL 611 #define GET_PStateImm0_15sList_DECL 612 #include "AArch64GenSystemOperands.inc" 613 614 struct PStateImm0_1 : SysAlias{ 615 using SysAlias::SysAlias; 616 }; 617 #define GET_PStateImm0_1Values_DECL 618 #define GET_PStateImm0_1sList_DECL 619 #include "AArch64GenSystemOperands.inc" 620 } 621 622 namespace AArch64PSBHint { 623 struct PSB : SysAlias { 624 using SysAlias::SysAlias; 625 }; 626 #define GET_PSBValues_DECL 627 #define GET_PSBsList_DECL 628 #include "AArch64GenSystemOperands.inc" 629 } 630 631 namespace AArch64PHint { 632 struct PHint { 633 const char *Name; 634 unsigned Encoding; 635 FeatureBitset FeaturesRequired; 636 637 bool haveFeatures(FeatureBitset ActiveFeatures) const { 638 return ActiveFeatures[llvm::AArch64::FeatureAll] || 639 (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 640 } 641 }; 642 643 #define GET_PHintValues_DECL 644 #define GET_PHintsList_DECL 645 #include "AArch64GenSystemOperands.inc" 646 647 const PHint *lookupPHintByName(StringRef); 648 const PHint *lookupPHintByEncoding(uint16_t); 649 } // namespace AArch64PHint 650 651 namespace AArch64BTIHint { 652 struct BTI : SysAlias { 653 using SysAlias::SysAlias; 654 }; 655 #define GET_BTIValues_DECL 656 #define GET_BTIsList_DECL 657 #include "AArch64GenSystemOperands.inc" 658 } 659 660 namespace AArch64SME { 661 enum ToggleCondition : unsigned { 662 Always, 663 IfCallerIsStreaming, 664 IfCallerIsNonStreaming 665 }; 666 } 667 668 namespace AArch64SE { 669 enum ShiftExtSpecifiers { 670 Invalid = -1, 671 LSL, 672 MSL, 673 LSR, 674 ASR, 675 ROR, 676 677 UXTB, 678 UXTH, 679 UXTW, 680 UXTX, 681 682 SXTB, 683 SXTH, 684 SXTW, 685 SXTX 686 }; 687 } 688 689 namespace AArch64Layout { 690 enum VectorLayout { 691 Invalid = -1, 692 VL_8B, 693 VL_4H, 694 VL_2S, 695 VL_1D, 696 697 VL_16B, 698 VL_8H, 699 VL_4S, 700 VL_2D, 701 702 // Bare layout for the 128-bit vector 703 // (only show ".b", ".h", ".s", ".d" without vector number) 704 VL_B, 705 VL_H, 706 VL_S, 707 VL_D 708 }; 709 } 710 711 inline static const char * 712 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) { 713 switch (Layout) { 714 case AArch64Layout::VL_8B: return ".8b"; 715 case AArch64Layout::VL_4H: return ".4h"; 716 case AArch64Layout::VL_2S: return ".2s"; 717 case AArch64Layout::VL_1D: return ".1d"; 718 case AArch64Layout::VL_16B: return ".16b"; 719 case AArch64Layout::VL_8H: return ".8h"; 720 case AArch64Layout::VL_4S: return ".4s"; 721 case AArch64Layout::VL_2D: return ".2d"; 722 case AArch64Layout::VL_B: return ".b"; 723 case AArch64Layout::VL_H: return ".h"; 724 case AArch64Layout::VL_S: return ".s"; 725 case AArch64Layout::VL_D: return ".d"; 726 default: llvm_unreachable("Unknown Vector Layout"); 727 } 728 } 729 730 inline static AArch64Layout::VectorLayout 731 AArch64StringToVectorLayout(StringRef LayoutStr) { 732 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr) 733 .Case(".8b", AArch64Layout::VL_8B) 734 .Case(".4h", AArch64Layout::VL_4H) 735 .Case(".2s", AArch64Layout::VL_2S) 736 .Case(".1d", AArch64Layout::VL_1D) 737 .Case(".16b", AArch64Layout::VL_16B) 738 .Case(".8h", AArch64Layout::VL_8H) 739 .Case(".4s", AArch64Layout::VL_4S) 740 .Case(".2d", AArch64Layout::VL_2D) 741 .Case(".b", AArch64Layout::VL_B) 742 .Case(".h", AArch64Layout::VL_H) 743 .Case(".s", AArch64Layout::VL_S) 744 .Case(".d", AArch64Layout::VL_D) 745 .Default(AArch64Layout::Invalid); 746 } 747 748 namespace AArch64SysReg { 749 struct SysReg { 750 const char Name[32]; 751 unsigned Encoding; 752 bool Readable; 753 bool Writeable; 754 FeatureBitset FeaturesRequired; 755 756 bool haveFeatures(FeatureBitset ActiveFeatures) const { 757 return ActiveFeatures[llvm::AArch64::FeatureAll] || 758 (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 759 } 760 }; 761 762 #define GET_SysRegsList_DECL 763 #define GET_SysRegValues_DECL 764 #include "AArch64GenSystemOperands.inc" 765 766 uint32_t parseGenericRegister(StringRef Name); 767 std::string genericRegisterString(uint32_t Bits); 768 } 769 770 namespace AArch64TLBI { 771 struct TLBI : SysAliasReg { 772 using SysAliasReg::SysAliasReg; 773 }; 774 #define GET_TLBITable_DECL 775 #include "AArch64GenSystemOperands.inc" 776 } 777 778 namespace AArch64II { 779 /// Target Operand Flag enum. 780 enum TOF { 781 //===------------------------------------------------------------------===// 782 // AArch64 Specific MachineOperand flags. 783 784 MO_NO_FLAG, 785 786 MO_FRAGMENT = 0x7, 787 788 /// MO_PAGE - A symbol operand with this flag represents the pc-relative 789 /// offset of the 4K page containing the symbol. This is used with the 790 /// ADRP instruction. 791 MO_PAGE = 1, 792 793 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of 794 /// that symbol within a 4K page. This offset is added to the page address 795 /// to produce the complete address. 796 MO_PAGEOFF = 2, 797 798 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high 799 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction 800 MO_G3 = 3, 801 802 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits 803 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction 804 MO_G2 = 4, 805 806 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits 807 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction 808 MO_G1 = 5, 809 810 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits 811 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction 812 MO_G0 = 6, 813 814 /// MO_HI12 - This flag indicates that a symbol operand represents the bits 815 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- 816 /// by-12-bits instruction. 817 MO_HI12 = 7, 818 819 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 820 /// reference is actually to the ".refptr.FOO" symbol. This is used for 821 /// stub symbols on windows. 822 MO_COFFSTUB = 0x8, 823 824 /// MO_GOT - This flag indicates that a symbol operand represents the 825 /// address of the GOT entry for the symbol, rather than the address of 826 /// the symbol itself. 827 MO_GOT = 0x10, 828 829 /// MO_NC - Indicates whether the linker is expected to check the symbol 830 /// reference for overflow. For example in an ADRP/ADD pair of relocations 831 /// the ADRP usually does check, but not the ADD. 832 MO_NC = 0x20, 833 834 /// MO_TLS - Indicates that the operand being accessed is some kind of 835 /// thread-local symbol. On Darwin, only one type of thread-local access 836 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the 837 /// referee will affect interpretation. 838 MO_TLS = 0x40, 839 840 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference 841 /// to the symbol is for an import stub. This is used for DLL import 842 /// storage class indication on Windows. 843 MO_DLLIMPORT = 0x80, 844 845 /// MO_S - Indicates that the bits of the symbol operand represented by 846 /// MO_G0 etc are signed. 847 MO_S = 0x100, 848 849 /// MO_PREL - Indicates that the bits of the symbol operand represented by 850 /// MO_G0 etc are PC relative. 851 MO_PREL = 0x200, 852 853 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag 854 /// in bits 56-63. 855 /// On a FrameIndex operand, indicates that the underlying memory is tagged 856 /// with an unknown tag value (MTE); this needs to be lowered either to an 857 /// SP-relative load or store instruction (which do not check tags), or to 858 /// an LDG instruction to obtain the tag value. 859 MO_TAGGED = 0x400, 860 861 /// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version 862 /// of a symbol, not the original. For dllimport symbols, this means it 863 /// uses "__imp_aux". For other symbols, this means it uses the mangled 864 /// ("#" prefix for C) name. 865 MO_ARM64EC_CALLMANGLE = 0x800, 866 }; 867 } // end namespace AArch64II 868 869 //===----------------------------------------------------------------------===// 870 // v8.3a Pointer Authentication 871 // 872 873 namespace AArch64PACKey { 874 enum ID : uint8_t { 875 IA = 0, 876 IB = 1, 877 DA = 2, 878 DB = 3, 879 LAST = DB 880 }; 881 } // namespace AArch64PACKey 882 883 /// Return 2-letter identifier string for numeric key ID. 884 inline static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID) { 885 switch (KeyID) { 886 case AArch64PACKey::IA: 887 return StringRef("ia"); 888 case AArch64PACKey::IB: 889 return StringRef("ib"); 890 case AArch64PACKey::DA: 891 return StringRef("da"); 892 case AArch64PACKey::DB: 893 return StringRef("db"); 894 } 895 llvm_unreachable("Unhandled AArch64PACKey::ID enum"); 896 } 897 898 /// Return numeric key ID for 2-letter identifier string. 899 inline static std::optional<AArch64PACKey::ID> 900 AArch64StringToPACKeyID(StringRef Name) { 901 if (Name == "ia") 902 return AArch64PACKey::IA; 903 if (Name == "ib") 904 return AArch64PACKey::IB; 905 if (Name == "da") 906 return AArch64PACKey::DA; 907 if (Name == "db") 908 return AArch64PACKey::DB; 909 return std::nullopt; 910 } 911 912 namespace AArch64 { 913 // The number of bits in a SVE register is architecturally defined 914 // to be a multiple of this value. If <M x t> has this number of bits, 915 // a <n x M x t> vector can be stored in a SVE register without any 916 // redundant bits. If <M x t> has this number of bits divided by P, 917 // a <n x M x t> vector is stored in a SVE register by placing index i 918 // in index i*P of a <n x (M*P) x t> vector. The other elements of the 919 // <n x (M*P) x t> vector (such as index 1) are undefined. 920 static constexpr unsigned SVEBitsPerBlock = 128; 921 static constexpr unsigned SVEMaxBitsPerVector = 2048; 922 } // end namespace AArch64 923 } // end namespace llvm 924 925 #endif 926