1 /* $NetBSD: grf_cv3dreg.h,v 1.13 2016/06/17 07:41:56 phx Exp $ */
2
3 /*
4 * Copyright (c) 1995 Michael Teske
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Ezra Story and by Kari
18 * Mettinen.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _GRF_CV3DREG_H
35 #define _GRF_CV3DREG_H
36
37 /*
38 * This is derived from Cirrus driver source.
39 */
40
41 /* Extension to grfvideo_mode to support text modes.
42 * This can be passed to both text & gfx functions
43 * without worry. If gv.depth == 4, then the extended
44 * fields for a text mode are present.
45 */
46
47 struct grfcv3dtext_mode {
48 struct grfvideo_mode gv;
49 unsigned short fx; /* font x dimension */
50 unsigned short fy; /* font y dimension */
51 unsigned short cols; /* screen dimensions */
52 unsigned short rows;
53 void *fdata; /* font data */
54 unsigned short fdstart;
55 unsigned short fdend;
56 };
57
58 /* read VGA register */
59 #define vgar(ba, reg) \
60 *(((volatile char *)ba)+(reg ^ 3))
61
62 /* write VGA register */
63 #define vgaw(ba, reg, val) \
64 *(((volatile char *)ba)+(reg ^ 3)) = ((val) & 0xff)
65
66 /* MMIO access */
67 #define ByteAccessIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) )
68
69 #define vgario(ba, reg) \
70 *(((volatile char *)ba) + ( ByteAccessIO(reg) ))
71
72 #define vgawio(ba, reg, val) \
73 do { \
74 if (!cv3d_zorroIII) { \
75 *(((volatile char *)cv3d_vcode_switch_base) + \
76 0x04) = (0x01 & 0xffff); \
77 __asm volatile ("nop"); \
78 } \
79 *(((volatile char *)cv3d_special_register_base) + \
80 ( ByteAccessIO(reg) & 0xffff )) = ((val) & 0xff); \
81 if (!cv3d_zorroIII) { \
82 *(((volatile char *)cv3d_vcode_switch_base) + \
83 0x04) = (0x02 & 0xffff); \
84 __asm volatile ("nop"); \
85 } \
86 } while (0)
87
88 /* read 32 Bit VGA register */
89 #define vgar32(ba, reg) \
90 *((volatile unsigned long *) (((volatile char *)ba)+reg))
91
92 /* write 32 Bit VGA register */
93 #define vgaw32(ba, reg, val) \
94 *((volatile unsigned long *) (((volatile char *)ba)+reg)) = val
95
96 /* read 16 Bit VGA register */
97 #define vgar16(ba, reg) \
98 *((volatile unsigned short *) (((volatile char *)ba)+reg))
99
100 /* write 16 Bit VGA register */
101 #define vgaw16(ba, reg, val) \
102 *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val
103
104 #define Select_Zorro2_FrameBuffer(flag) \
105 do { \
106 *(((volatile char *)cv3d_vcode_switch_base) + \
107 0x08) = ((flag * 0x40) & 0xffff); \
108 __asm volatile ("nop"); \
109 } while (0)
110
111 int grfcv3d_cnprobe(void);
112 void grfcv3d_iteinit(struct grf_softc *);
113 static inline void GfxBusyWait(volatile void *);
114 static inline void GfxFifoWait(volatile void *);
115 static inline unsigned char RAttr(volatile void *, short);
116 static inline unsigned char RSeq(volatile void *, short);
117 static inline unsigned char RCrt(volatile void *, short);
118 static inline unsigned char RGfx(volatile void *, short);
119
120
121 /*
122 * defines for the used register addresses (mw)
123 *
124 * NOTE: there are some registers that have different addresses when
125 * in mono or color mode. We only support color mode, and thus
126 * some addresses won't work in mono-mode!
127 *
128 * General and VGA-registers taken from retina driver. Fixed a few
129 * bugs in it. (SR and GR read address is Port + 1, NOT Port)
130 *
131 */
132
133 /* General Registers: */
134 #define GREG_MISC_OUTPUT_R 0x03CC
135 #define GREG_MISC_OUTPUT_W 0x03C2
136 #define GREG_FEATURE_CONTROL_R 0x03CA
137 #define GREG_FEATURE_CONTROL_W 0x03DA
138 #define GREG_INPUT_STATUS0_R 0x03C2
139 #define GREG_INPUT_STATUS1_R 0x03DA
140
141 /* Setup Registers: */
142 #define SREG_OPTION_SELECT 0x0102
143 #define SREG_VIDEO_SUBS_ENABLE 0x03C3 /* Trio64: 0x46E8 */
144
145 /* Attribute Controller: */
146 #define ACT_ADDRESS 0x03C0
147 #define ACT_ADDRESS_R 0x03C1
148 #define ACT_ADDRESS_W 0x03C0
149 #define ACT_ADDRESS_RESET 0x03DA
150 #define ACT_ID_PALETTE0 0x00
151 #define ACT_ID_PALETTE1 0x01
152 #define ACT_ID_PALETTE2 0x02
153 #define ACT_ID_PALETTE3 0x03
154 #define ACT_ID_PALETTE4 0x04
155 #define ACT_ID_PALETTE5 0x05
156 #define ACT_ID_PALETTE6 0x06
157 #define ACT_ID_PALETTE7 0x07
158 #define ACT_ID_PALETTE8 0x08
159 #define ACT_ID_PALETTE9 0x09
160 #define ACT_ID_PALETTE10 0x0A
161 #define ACT_ID_PALETTE11 0x0B
162 #define ACT_ID_PALETTE12 0x0C
163 #define ACT_ID_PALETTE13 0x0D
164 #define ACT_ID_PALETTE14 0x0E
165 #define ACT_ID_PALETTE15 0x0F
166 #define ACT_ID_ATTR_MODE_CNTL 0x10
167 #define ACT_ID_OVERSCAN_COLOR 0x11
168 #define ACT_ID_COLOR_PLANE_ENA 0x12
169 #define ACT_ID_HOR_PEL_PANNING 0x13
170 #define ACT_ID_COLOR_SELECT 0x14 /* ACT_ID_PIXEL_PADDING */
171
172 /* Graphics Controller: */
173 #define GCT_ADDRESS 0x03CE
174 #define GCT_ADDRESS_R 0x03CF
175 #define GCT_ADDRESS_W 0x03CF
176 #define GCT_ID_SET_RESET 0x00
177 #define GCT_ID_ENABLE_SET_RESET 0x01
178 #define GCT_ID_COLOR_COMPARE 0x02
179 #define GCT_ID_DATA_ROTATE 0x03
180 #define GCT_ID_READ_MAP_SELECT 0x04
181 #define GCT_ID_GRAPHICS_MODE 0x05
182 #define GCT_ID_MISC 0x06
183 #define GCT_ID_COLOR_XCARE 0x07
184 #define GCT_ID_BITMASK 0x08
185
186 /* Sequencer: */
187 #define SEQ_ADDRESS 0x03C4
188 #define SEQ_ADDRESS_R 0x03C5
189 #define SEQ_ADDRESS_W 0x03C5
190 #define SEQ_ID_RESET 0x00
191 #define SEQ_ID_CLOCKING_MODE 0x01
192 #define SEQ_ID_MAP_MASK 0x02
193 #define SEQ_ID_CHAR_MAP_SELECT 0x03
194 #define SEQ_ID_MEMORY_MODE 0x04
195 #define SEQ_ID_UNKNOWN1 0x05
196 #define SEQ_ID_UNKNOWN2 0x06
197 #define SEQ_ID_UNKNOWN3 0x07
198 /* S3 extensions */
199 #define SEQ_ID_UNLOCK_EXT 0x08
200 #define SEQ_ID_MMIO_SELECT 0x09 /* Trio64: SEQ_ID_EXT_SEQ_REG9 */
201 #define SEQ_ID_BUS_REQ_CNTL 0x0A
202 #define SEQ_ID_EXT_MISC_SEQ 0x0B
203 #define SEQ_ID_UNKNOWN4 0x0C
204 #define SEQ_ID_EXT_SEQ 0x0D
205 #define SEQ_ID_UNKNOWN5 0x0E
206 #define SEQ_ID_UNKNOWN6 0x0F
207 #define SEQ_ID_MCLK_LO 0x10
208 #define SEQ_ID_MCLK_HI 0x11
209 #define SEQ_ID_DCLK_LO 0x12
210 #define SEQ_ID_DCLK_HI 0x13
211 #define SEQ_ID_CLKSYN_CNTL_1 0x14
212 #define SEQ_ID_CLKSYN_CNTL_2 0x15
213 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */
214 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */
215 #define SEQ_ID_RAMDAC_CNTL 0x18
216 #define SEQ_ID_MORE_MAGIC 0x1A /* not available on the Virge */
217 #define SEQ_ID_SIGNAL_SELECT 0x1C
218
219 /* CRT Controller: */
220 #define CRT_ADDRESS 0x03D4
221 #define CRT_ADDRESS_R 0x03D5
222 #define CRT_ADDRESS_W 0x03D5
223 #define CRT_ID_HOR_TOTAL 0x00
224 #define CRT_ID_HOR_DISP_ENA_END 0x01
225 #define CRT_ID_START_HOR_BLANK 0x02
226 #define CRT_ID_END_HOR_BLANK 0x03
227 #define CRT_ID_START_HOR_RETR 0x04
228 #define CRT_ID_END_HOR_RETR 0x05
229 #define CRT_ID_VER_TOTAL 0x06
230 #define CRT_ID_OVERFLOW 0x07
231 #define CRT_ID_PRESET_ROW_SCAN 0x08
232 #define CRT_ID_MAX_SCAN_LINE 0x09
233 #define CRT_ID_CURSOR_START 0x0A
234 #define CRT_ID_CURSOR_END 0x0B
235 #define CRT_ID_START_ADDR_HIGH 0x0C
236 #define CRT_ID_START_ADDR_LOW 0x0D
237 #define CRT_ID_CURSOR_LOC_HIGH 0x0E
238 #define CRT_ID_CURSOR_LOC_LOW 0x0F
239 #define CRT_ID_START_VER_RETR 0x10
240 #define CRT_ID_END_VER_RETR 0x11
241 #define CRT_ID_VER_DISP_ENA_END 0x12
242 #define CRT_ID_SCREEN_OFFSET 0x13
243 #define CRT_ID_UNDERLINE_LOC 0x14
244 #define CRT_ID_START_VER_BLANK 0x15
245 #define CRT_ID_END_VER_BLANK 0x16
246 #define CRT_ID_MODE_CONTROL 0x17
247 #define CRT_ID_LINE_COMPARE 0x18
248 #define CRT_ID_GD_LATCH_RBACK 0x22
249 #define CRT_ID_ACT_TOGGLE_RBACK 0x24
250 #define CRT_ID_ACT_INDEX_RBACK 0x26
251 /* S3 extensions: S3 VGA Registers */
252 #define CRT_ID_DEVICE_HIGH 0x2D
253 #define CRT_ID_DEVICE_LOW 0x2E
254 #define CRT_ID_REVISION 0x2F
255 #define CRT_ID_CHIP_ID_REV 0x30
256 #define CRT_ID_MEMORY_CONF 0x31
257 #define CRT_ID_BACKWAD_COMP_1 0x32
258 #define CRT_ID_BACKWAD_COMP_2 0x33
259 #define CRT_ID_BACKWAD_COMP_3 0x34
260 #define CRT_ID_REGISTER_LOCK 0x35
261 #define CRT_ID_CONFIG_1 0x36
262 #define CRT_ID_CONFIG_2 0x37
263 #define CRT_ID_REGISTER_LOCK_1 0x38
264 #define CRT_ID_REGISTER_LOCK_2 0x39
265 #define CRT_ID_MISC_1 0x3A
266 #define CRT_ID_DISPLAY_FIFO 0x3B
267 #define CRT_ID_LACE_RETR_START 0x3C
268 /* S3 extensions: System Control Registers */
269 #define CRT_ID_SYSTEM_CONFIG 0x40
270 #define CRT_ID_BIOS_FLAG 0x41
271 #define CRT_ID_LACE_CONTROL 0x42
272 #define CRT_ID_EXT_MODE 0x43
273 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */
274 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46
275 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47
276 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48
277 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49
278 #define CRT_ID_HWGC_FG_STACK 0x4A
279 #define CRT_ID_HWGC_BG_STACK 0x4B
280 #define CRT_ID_HWGC_START_AD_HI 0x4C
281 #define CRT_ID_HWGC_START_AD_LO 0x4D
282 #define CRT_ID_HWGC_DSTART_X 0x4E
283 #define CRT_ID_HWGC_DSTART_Y 0x4F
284 /* S3 extensions: System Extension Registers */
285 #define CRT_ID_EXT_SYS_CNTL_1 0x50
286 #define CRT_ID_EXT_SYS_CNTL_2 0x51
287 #define CRT_ID_EXT_BIOS_FLAG_1 0x52
288 #define CRT_ID_EXT_MEM_CNTL_1 0x53
289 #define CRT_ID_EXT_MEM_CNTL_2 0x54
290 #define CRT_ID_EXT_DAC_CNTL 0x55
291 #define CRT_ID_EX_SYNC_1 0x56
292 #define CRT_ID_EX_SYNC_2 0x57
293 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */
294 #define CRT_ID_LAW_POS_HI 0x59
295 #define CRT_ID_LAW_POS_LO 0x5A
296 #define CRT_ID_GOUT_PORT 0x5C
297 #define CRT_ID_EXT_HOR_OVF 0x5D
298 #define CRT_ID_EXT_VER_OVF 0x5E
299 #define CRT_ID_EXT_MEM_CNTL_3 0x60
300 #define CRT_ID_EXT_MEM_CNTL_4 0x61 /* only available on the Virge */
301 #define CRT_ID_EX_SYNC_3 0x63 /* not available on the Virge */
302 #define CRT_ID_EXT_MISC_CNTL 0x65
303 #define CRT_ID_EXT_MISC_CNTL_1 0x66
304 #define CRT_ID_EXT_MISC_CNTL_2 0x67
305 #define CRT_ID_CONFIG_3 0x68
306 #define CRT_ID_EXT_SYS_CNTL_3 0x69
307 #define CRT_ID_EXT_SYS_CNTL_4 0x6A
308 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B
309 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C
310 #define CRT_ID_EXT_BIOS_FLAG_5 0x6D /* only available on the Virge */
311 #define CRT_ID_RAMDAC_SIG_TEST 0x6E /* only available on the Virge */
312 #define CRT_ID_CONFIG_4 0x6F /* only available on the Virge */
313
314 /* Streams Processor */
315 #define SP_PRIMARY_CONTROL 0x8180
316 #define SP_COLOR_CHROMA_KEY_CONTROL 0x8184
317 #define SP_SECONDARY_CONTROL 0x8190
318 #define SP_CHROMA_KEY_UPPER_BOUND 0x8194
319 #define SP_SECONDARY_CONSTANTS 0x8198
320 #define SP_BLEND_CONTROL 0x81A0
321 #define SP_PRIMARY_ADDRESS_0 0x81C0
322 #define SP_PRIMARY_ADDRESS_1 0x81C4
323 #define SP_PRIMARY_STRIDE 0x81C8
324 #define SP_DOUBLE_BUFFER_LPB_SUPPORT 0x81CC
325 #define SP_SECONDARY_ADDRESS_0 0x81D0
326 #define SP_SECONDARY_ADDRESS_1 0x81D4
327 #define SP_SECONDARY_STRIDE 0x81D8
328 #define SP_OPAQUE_OVERLAY_CONTROL 0x81DC
329 #define SP_K1_VERTICAL_SCALE_FACTOR 0x81E0
330 #define SP_K2_VERTICAL_SCALE_FACTOR 0x81E4
331 #define SP_DDA_VERTICAL_ACCUMULATOR 0x81E8
332 #define SP_FIFO_CONTROL 0x81EC
333 #define SP_PRIMARY_WINDOW_TOP_LEFT 0x81F0
334 #define SP_PRIMARY_WINDOW_SIZE 0x81F4
335 #define SP_SECONDARY_WINDOW_TOP_LEFT 0x81F8
336 #define SP_SECONDARY_WINDOW_SIZE 0x81FC
337
338 /* Memory Port Controller */
339 #define MPC_FIFO_CONTROL 0x8200
340 #define MPC_MIU_CONTROL 0x8204
341 #define MPC_STREAMS_TIMEOUT 0x8208
342 #define MPC_MISC_TIMEOUT 0x820C
343 #define MPC_DMA_READ_BASE_ADDRESS 0x8220
344 #define MPC_DMA_READ_STRIDE_WIDTH 0x8224
345
346 /* Miscellaneous Registers */
347 #define MR_SUBSYSTEM_STATUS_CNTL 0x8504
348 #define MR_ADVANCED_FUNCTION_CONTROL 0x850C
349
350 /* S3d Engine */
351 #define S3D_BIT_BLT_RECT_FILL 0xA400
352 #define S3D_LINE_2D 0xA800
353 #define S3D_POLYGON_2D 0xAC00
354 #define S3D_LINE_3D 0xB000
355 #define S3D_TRIANGLE_3D 0xB400
356
357 #define BLT_ADDRESS 0xA4D4
358 #define BLT_SOURCE_ADDRESS 0xA4D4
359 #define BLT_DEST_ADDRESS 0xA4D8
360 #define BLT_CLIP_LEFT_RIGHT 0xA4DC
361 #define BLT_CLIP_LEFT BLT_CLIP_LEFT_RIGHT
362 #define BLT_CLIP_RIGHT 0xA4DE
363 #define BLT_CLIP_TOP_BOTTOM 0xA4E0
364 #define BLT_CLIP_BOTTOM BLT_CLIP_TOP_BOTTOM
365 #define BLT_CLIP_TOP 0xA4E2
366 #define BLT_DEST_SOURCE_PITCH 0xA4E4
367 #define BLT_SOURCE_PITCH BLT_DEST_SOURCE_PITCH
368 #define BLT_DEST_PITCH 0xA4E6
369 #define BLT_MONO_PATTERN 0xA4E8
370 #define BLT_MONO_PATTERN_0 BLT_MONO_PATTERN
371 #define BLT_MONO_PATTERN_1 0xA4EC
372 #define BLT_PATTERN_BG_COLOR 0xA4F0
373 #define BLT_PATTERN_BG_COLOR_TRUE_COLOR BLT_PATTERN_BG_COLOR
374 #define BLT_PATTERN_BG_COLOR_ALPHA BLT_PATTERN_BG_COLOR
375 #define BLT_PATTERN_BG_COLOR_RED 0xA4F1
376 #define BLT_PATTERN_BG_COLOR_HI_COLOR 0xA4F2
377 #define BLT_PATTERN_BG_COLOR_GREEN BLT_PATTERN_BG_COLOR_HI_COLOR
378 #define BLT_PATTERN_BG_COLOR_INDEX 0xA4F3
379 #define BLT_PATTERN_BG_COLOR_BLUE BLT_PATTERN_BG_COLOR_INDEX
380 #define BLT_PATTERN_FG_COLOR 0xA4F4
381 #define BLT_PATTERN_FG_COLOR_TRUE_COLOR BLT_PATTERN_FG_COLOR
382 #define BLT_PATTERN_FG_COLOR_ALPHA BLT_PATTERN_FG_COLOR
383 #define BLT_PATTERN_FG_COLOR_RED 0xA4F5
384 #define BLT_PATTERN_FG_COLOR_HI_COLOR 0xA4F6
385 #define BLT_PATTERN_FG_COLOR_GREEN BLT_PATTERN_FG_COLOR_HI_COLOR
386 #define BLT_PATTERN_FG_COLOR_INDEX 0xA4F7
387 #define BLT_PATTERN_FG_COLOR_BLUE BLT_PATTERN_FG_COLOR_INDEX
388 #define BLT_SOURCE_BG_COLOR 0xA4F8
389 #define BLT_SOURCE_BG_COLOR_TRUE_COLOR BLT_SOURCE_BG_COLOR
390 #define BLT_SOURCE_BG_COLOR_ALPHA BLT_SOURCE_BG_COLOR
391 #define BLT_SOURCE_BG_COLOR_RED 0xA4F9
392 #define BLT_SOURCE_BG_COLOR_HI_COLOR 0xA4FA
393 #define BLT_SOURCE_BG_COLOR_GREEN BLT_SOURCE_BG_COLOR_HI_COLOR
394 #define BLT_SOURCE_BG_COLOR_INDEX 0xA4FB
395 #define BLT_SOURCE_BG_COLOR_BLUE BLT_SOURCE_BG_COLOR_INDEX
396 #define BLT_SOURCE_FG_COLOR 0xA4FC
397 #define BLT_SOURCE_FG_COLOR_TRUE_COLOR BLT_SOURCE_FG_COLOR
398 #define BLT_SOURCE_FG_COLOR_ALPHA BLT_SOURCE_FG_COLOR
399 #define BLT_SOURCE_FG_COLOR_RED 0xA4FD
400 #define BLT_SOURCE_FG_COLOR_HI_COLOR 0xA4FE
401 #define BLT_SOURCE_FG_COLOR_GREEN BLT_SOURCE_FG_COLOR_HI_COLOR
402 #define BLT_SOURCE_FG_COLOR_INDEX 0xA4FF
403 #define BLT_SOURCE_FG_COLOR_BLUE BLT_SOURCE_FG_COLOR_INDEX
404 #define BLT_COMMAND_SET 0xA500
405 #define BLT_WIDTH_HEIGHT 0xA504
406 #define BLT_HEIGHT BLT_WIDTH_HEIGHT
407 #define BLT_WIDTH 0xA506
408 #define BLT_SOURCE_XY 0xA508
409 #define BLT_SOURCE_Y BLT_SOURCE_XY
410 #define BLT_SOURCE_X 0xA50A
411 #define BLT_DESTINATION_XY 0xA50C
412 #define BLT_DESTINATION_Y BLT_DESTINATION_XY
413 #define BLT_DESTINATION_X 0xA50E
414
415 #define L2D_ADDRESS 0xA8D4
416 #define L2D_SOURCE_ADDRESS 0xA8D4
417 #define L2D_DEST_ADDRESS 0xA8D8
418 #define L2D_CLIP_LEFT_RIGHT 0xA8DC
419 #define L2D_CLIP_LEFT L2D_CLIP_LEFT_RIGHT
420 #define L2D_CLIP_RIGHT 0xA8DE
421 #define L2D_CLIP_TOP_BOTTOM 0xA8E0
422 #define L2D_CLIP_BOTTOM L2D_CLIP_TOP_BOTTOM
423 #define L2D_CLIP_TOP 0xA8E2
424 #define L2D_DEST_SOURCE_PITCH 0xA8E4
425 #define L2D_SOURCE_PITCH L2D_DEST_SOURCE_PITCH
426 #define L2D_DEST_PITCH 0xA8E6
427 #define L2D_PAD_0 0xA8E8
428 #define L2D_PATTERN_FG_COLOR_TRUE_COLOR 0xA8F4
429 #define L2D_PATTERN_FG_COLOR_ALPHA L2D_PATTERN_FG_COLOR_TRUECOLOR
430 #define L2D_PATTERN_FG_COLOR_RED 0xA8F5
431 #define L2D_PATTERN_FG_COLOR_HI_COLOR 0xA8F6
432 #define L2D_PATTERN_FG_COLOR_GREEN L2D_PATTERN_FG_COLOR_HICOLOR
433 #define L2D_PATTERN_FG_COLOR_INDEX 0xA8F7
434 #define L2D_PATTERN_FG_COLOR_BLUE L2D_PATTERN_FG_COLOR_INDEX
435 #define L2D_PAD_1 0xA8F8
436 #define L2D_COMMAND_SET 0xA900
437 #define L2D_PAD_2 0xA904
438 #define L2D_END_0_END_1 0xA96C
439 #define L2D_END_1 L2D_END_0_END_1
440 #define L2D_END_0 0xA96E
441 #define L2D_DX 0xA970
442 #define L2D_X_START 0xA974
443 #define L2D_Y_START 0xA978
444 #define L2D_Y_COUNT 0xA97C
445
446 #define P2D_ADDRESS 0xACD4
447 #define P2D_SOURCE_ADDRESS 0xACD4
448 #define P2D_DEST_ADDRESS 0xACD8
449 #define P2D_CLIP_LEFT_RIGHT 0xACDC
450 #define P2D_CLIP_LEFT P2D_CLIP_LEFT_RIGHT
451 #define P2D_CLIP_RIGHT 0xACDE
452 #define P2D_CLIP_TOP_BOTTOM 0xACE0
453 #define P2D_CLIP_BOTTOM P2D_CLIP_TOP_BOTTOM
454 #define P2D_CLIP_TOP 0xACE2
455 #define P2D_DEST_SOURCE_PITCH 0xACE4
456 #define P2D_SOURCE_PITCH P2D_DEST_SOURCE_PITCH
457 #define P2D_DEST_PITCH 0xACE6
458 #define P2D_MONO_PATTERN 0xACE8
459 #define P2D_PATTERN_BG_COLOR_TRUE_COLOR 0xACF0
460 #define P2D_PATTERN_BG_COLOR_ALPHA P2D_PATTERN_BG_COLOR_TRUE_COLOR
461 #define P2D_PATTERN_BG_COLOR_RED 0xACF1
462 #define P2D_PATTERN_BG_COLOR_HI_COLOR 0xACF2
463 #define P2D_PATTERN_BG_COLOR_GREEN P2D_PATTERN_BG_COLOR_HI_COLOR
464 #define P2D_PATTERN_BG_COLOR_INDEX 0xACF3
465 #define P2D_PATTERN_BG_COLOR_BLUE P2D_PATTERN_BG_COLOR_INDEX
466 #define P2D_PATTERN_FG_COLOR_TRUE_COLOR 0xACF4
467 #define P2D_PATTERN_FG_COLOR_ALPHA P2D_PATTERN_FG_COLOR_TRUE_COLOR
468 #define P2D_PATTERN_FG_COLOR_RED 0xACF5
469 #define P2D_PATTERN_FG_COLOR_HI_COLOR 0xACF6
470 #define P2D_PATTERN_FG_COLOR_GREEN P2D_PATTERN_FG_COLOR_HI_COLOR
471 #define P2D_PATTERN_FG_COLOR_INDEX 0xACF7
472 #define P2D_PATTERN_FG_COLOR_BLUE P2D_PATTERN_FG_COLOR_INDEX
473 #define P2D_PAD_1 0xACF8
474 #define P2D_COMMAND_SET 0xAD00
475 #define P2D_PAD_2 0xAD04
476 #define P2D_RIGHT_DX 0xAD68
477 #define P2D_RIGHT_X_START 0xAD6C
478 #define P2D_LEFT_DX 0xAD70
479 #define P2D_LEFT_X_START 0xAD74
480 #define P2D_Y_START 0xAD78
481 #define P2D_Y_COUNT 0xAD7C
482
483 #define CMD_NOP (7 << 27) /* %1111 << 27 */
484 #define CMD_LINE (3 << 27) /* %0011 << 27 */
485 #define CMD_RECT (4 << 27) /* %0010 << 27 */
486 #define CMD_POLYGON (5 << 27) /* %0101 << 27 */
487 #define CMD_BITBLT (0 << 27) /* %0000 << 27 */
488
489 #define CMD_SKIP_TRANSFER_BYTES_1 (1 << 12) /* %01 << 12 */
490 #define CMD_SKIP_TRANSFER_BYTES_2 (2 << 12) /* %10 << 12 */
491 #define CMD_SKIP_TRANSFER_BYTES_3 (3 << 12) /* %11 << 12 */
492
493 #define CMD_TRANSFER_ALIGNMENT_BYTE (0 << 10) /* %00 << 10 */
494 #define CMD_TRANSFER_ALIGNMENT_WORD (1 << 10) /* %01 << 10 */
495 #define CMD_TRANSFER_ALIGNMENT_DOUBLEWORD (2 << 10) /* %10 << 10 */
496
497 #define CMD_CHUNKY (0 << 2) /* %00 << 2 */
498 #define CMD_HI_COLOR (1 << 2) /* %01 << 2 */
499 #define CMD_TRUE_COLOR (2 << 2) /* %10 << 2 */
500
501 #define ROP_FALSE 0x00
502 #define ROP_NOR 0x10
503 #define ROP_ONLYDST 0x20
504 #define ROP_NOTSRC 0x30
505 #define ROP_ONLYSRC 0x40
506 #define ROP_NOTDST 0x50
507 #define ROP_EOR 0x60
508 #define ROP_NAND 0x70
509 #define ROP_AND 0x80
510 #define ROP_NEOR 0x90
511 #define ROP_DST 0xA0
512 #define ROP_NOTONLYSRC 0xB0
513 #define ROP_SRC 0xC0
514 #define ROP_NOTONLYDST 0xD0
515 #define ROP_OR 0xE0
516 #define ROP_TRUE 0xF0
517
518 /* Pass-through */
519 #if 0 /* XXX */
520 #define PASS_ADDRESS 0x
521 #define PASS_ADDRESS_W 0x
522 #endif
523
524 /* Video DAC */
525 #define VDAC_ADDRESS 0x03C8
526 #define VDAC_ADDRESS_W 0x03C8
527 #define VDAC_ADDRESS_R 0x03C7
528 #define VDAC_STATE 0x03C7
529 #define VDAC_DATA 0x03C9
530 #define VDAC_MASK 0x03C6
531
532
533 #define WGfx(ba, idx, val) \
534 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0)
535
536 #define WSeq(ba, idx, val) \
537 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0)
538
539 #define WCrt(ba, idx, val) \
540 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0)
541
542 #define WAttr(ba, idx, val) \
543 do { \
544 unsigned char tmp;\
545 tmp = vgar(ba, ACT_ADDRESS_RESET);\
546 __USE(tmp);\
547 vgaw(ba, ACT_ADDRESS_W, idx);\
548 vgaw(ba, ACT_ADDRESS_W, val);\
549 } while (0)
550
551
552 #define SetTextPlane(ba, m) \
553 do { \
554 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\
555 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\
556 } while (0)
557
558
559 /* Gfx engine busy wait */
560
561 static inline void
GfxBusyWait(volatile void * ba)562 GfxBusyWait (volatile void *ba)
563 {
564 int test;
565
566 do {
567 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL);
568 __asm volatile ("nop");
569 } while (!(test & (1 << 13)));
570 }
571
572
573 static inline void
GfxFifoWait(volatile void * ba)574 GfxFifoWait(volatile void *ba)
575 {
576 #if 0 /* XXX */
577 int test;
578
579 do {
580 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL);
581 } while (test & 0x0f);
582 #endif
583 }
584
585
586 /* Special wakeup/passthrough registers on graphics boards
587 *
588 * The methods have diverged a bit for each board, so
589 * WPass(P) has been converted into a set of specific
590 * inline functions.
591 */
592
593 static inline unsigned char
RAttr(volatile void * ba,short idx)594 RAttr(volatile void *ba, short idx)
595 {
596
597 vgaw(ba, ACT_ADDRESS_W, idx);
598 delay(0);
599 return vgar(ba, ACT_ADDRESS_R);
600 }
601
602 static inline unsigned char
RSeq(volatile void * ba,short idx)603 RSeq(volatile void *ba, short idx)
604 {
605 vgaw(ba, SEQ_ADDRESS, idx);
606 return vgar(ba, SEQ_ADDRESS_R);
607 }
608
609 static inline unsigned char
RCrt(volatile void * ba,short idx)610 RCrt(volatile void *ba, short idx)
611 {
612 vgaw(ba, CRT_ADDRESS, idx);
613 return vgar(ba, CRT_ADDRESS_R);
614 }
615
616 static inline unsigned char
RGfx(volatile void * ba,short idx)617 RGfx(volatile void *ba, short idx)
618 {
619 vgaw(ba, GCT_ADDRESS, idx);
620 return vgar(ba, GCT_ADDRESS_R);
621 }
622
623 #endif /* _GRF_CV3DREG_H */
624