1 //===---------------------- InOrderIssueStage.h -----------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// 10 /// InOrderIssueStage implements an in-order execution pipeline. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_MCA_IN_ORDER_ISSUE_STAGE_H 15 #define LLVM_MCA_IN_ORDER_ISSUE_STAGE_H 16 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/MCA/SourceMgr.h" 19 #include "llvm/MCA/Stages/Stage.h" 20 21 #include <queue> 22 23 namespace llvm { 24 struct MCSchedModel; 25 class MCSubtargetInfo; 26 27 namespace mca { 28 class RegisterFile; 29 class ResourceManager; 30 31 class InOrderIssueStage final : public Stage { 32 const MCSchedModel &SM; 33 const MCSubtargetInfo &STI; 34 RegisterFile &PRF; 35 std::unique_ptr<ResourceManager> RM; 36 37 /// Instructions that were issued, but not executed yet. 38 SmallVector<InstRef, 4> IssuedInst; 39 40 /// Number of instructions issued in the current cycle. 41 unsigned NumIssued; 42 43 /// If an instruction cannot execute due to an unmet register or resource 44 /// dependency, the it is stalled for StallCyclesLeft. 45 InstRef StalledInst; 46 unsigned StallCyclesLeft; 47 48 /// Instruction that is issued in more than 1 cycle. 49 InstRef CarriedOver; 50 /// Number of CarriedOver uops left to issue. 51 unsigned CarryOver; 52 53 /// Number of instructions that can be issued in the current cycle. 54 unsigned Bandwidth; 55 56 /// Number of cycles (counted from the current cycle) until the last write is 57 /// committed. This is taken into account to ensure that writes commit in the 58 /// program order. 59 unsigned LastWriteBackCycle; 60 61 InOrderIssueStage(const InOrderIssueStage &Other) = delete; 62 InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete; 63 64 /// If IR has an unmet register or resource dependency, canExecute returns 65 /// false. StallCycles is set to the number of cycles left before the 66 /// instruction can be issued. 67 bool canExecute(const InstRef &IR, unsigned *StallCycles) const; 68 69 /// Issue the instruction, or update StallCycles if IR is stalled. 70 Error tryIssue(InstRef &IR, unsigned *StallCycles); 71 72 /// Update status of instructions from IssuedInst. 73 void updateIssuedInst(); 74 75 /// Continue to issue the CarriedOver instruction. 76 void updateCarriedOver(); 77 78 /// Retire instruction once it is executed. 79 void retireInstruction(InstRef &IR); 80 81 public: InOrderIssueStage(RegisterFile & PRF,const MCSchedModel & SM,const MCSubtargetInfo & STI)82 InOrderIssueStage(RegisterFile &PRF, const MCSchedModel &SM, 83 const MCSubtargetInfo &STI) 84 : SM(SM), STI(STI), PRF(PRF), RM(std::make_unique<ResourceManager>(SM)), 85 NumIssued(0), StallCyclesLeft(0), CarryOver(0), Bandwidth(0), 86 LastWriteBackCycle(0) {} 87 88 bool isAvailable(const InstRef &) const override; 89 bool hasWorkToComplete() const override; 90 Error execute(InstRef &IR) override; 91 Error cycleStart() override; 92 Error cycleEnd() override; 93 }; 94 95 } // namespace mca 96 } // namespace llvm 97 98 #endif // LLVM_MCA_IN_ORDER_ISSUE_STAGE_H 99