1 /* microblaze-opcm.h -- Header used in microblaze-opc.h 2 3 Copyright (C) 2009-2024 Free Software Foundation, Inc. 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 23 #ifndef MICROBLAZE_OPCM 24 #define MICROBLAZE_OPCM 25 26 enum microblaze_instr 27 { 28 add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu, 29 addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, 30 mulh, mulhu, mulhsu, swapb, swaph, 31 idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, 32 ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului, 33 /* 'or/and/xor' are C++ keywords. */ 34 microblaze_or, microblaze_and, microblaze_xor, 35 andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, 36 wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse, 37 mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, 38 bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, 39 imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, 40 brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, 41 bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx, 42 sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, 43 sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, 44 fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, 45 /* 'fsqrt' is a glibc:math.h symbol. */ 46 fint, microblaze_fsqrt, 47 tget, tcget, tnget, tncget, tput, tcput, tnput, tncput, 48 eget, ecget, neget, necget, eput, ecput, neput, necput, 49 teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput, 50 aget, caget, naget, ncaget, aput, caput, naput, ncaput, 51 taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput, 52 eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput, 53 teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput, 54 getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd, 55 putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd, 56 egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd, 57 eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd, 58 agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd, 59 aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, 60 eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, 61 eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, 62 invalid_inst 63 }; 64 65 enum microblaze_instr_type 66 { 67 arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst, 68 return_inst, immediate_inst, special_inst, memory_load_inst, 69 memory_store_inst, barrel_shift_inst, anyware_inst 70 }; 71 72 #define INST_WORD_SIZE 4 73 74 /* Gen purpose regs go from 0 to 31. */ 75 /* Mask is reg num - max_reg_num, ie reg_num - 32 in this case. */ 76 77 #define REG_PC_MASK 0x8000 78 #define REG_MSR_MASK 0x8001 79 #define REG_EAR_MASK 0x8003 80 #define REG_ESR_MASK 0x8005 81 #define REG_FSR_MASK 0x8007 82 #define REG_BTR_MASK 0x800b 83 #define REG_EDR_MASK 0x800d 84 #define REG_PVR_MASK 0xa000 85 #define REG_SLR_MASK 0x8800 86 #define REG_SHR_MASK 0x8802 87 88 #define REG_PID_MASK 0x9000 89 #define REG_ZPR_MASK 0x9001 90 #define REG_TLBX_MASK 0x9002 91 #define REG_TLBLO_MASK 0x9003 92 #define REG_TLBHI_MASK 0x9004 93 #define REG_TLBSX_MASK 0x9005 94 95 #define MIN_REGNUM 0 96 #define MAX_REGNUM 31 97 98 #define MIN_PVR_REGNUM 0 99 #define MAX_PVR_REGNUM 15 100 101 #define REG_PC 32 /* PC. */ 102 #define REG_MSR 33 /* Machine status reg. */ 103 #define REG_EAR 35 /* Exception reg. */ 104 #define REG_ESR 37 /* Exception reg. */ 105 #define REG_FSR 39 /* FPU Status reg. */ 106 #define REG_BTR 43 /* Branch Target reg. */ 107 #define REG_EDR 45 /* Exception reg. */ 108 #define REG_SHR 50 /* Stack High reg. */ 109 #define REG_SLR 51 /* Stack Low reg. */ 110 #define REG_PVR 40960 /* Program Verification reg. */ 111 112 #define REG_PID 36864 /* MMU: Process ID reg. */ 113 #define REG_ZPR 36865 /* MMU: Zone Protect reg. */ 114 #define REG_TLBX 36866 /* MMU: TLB Index reg. */ 115 #define REG_TLBLO 36867 /* MMU: TLB Low reg. */ 116 #define REG_TLBHI 36868 /* MMU: TLB High reg. */ 117 #define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */ 118 119 /* Alternate names for gen purpose regs. */ 120 #define REG_SP 1 /* stack pointer. */ 121 #define REG_ROSDP 2 /* read-only small data pointer. */ 122 #define REG_RWSDP 13 /* read-write small data pointer. */ 123 124 /* Assembler Register - Used in Delay Slot Optimization. */ 125 #define REG_AS 18 126 #define REG_ZERO 0 127 128 #define RD_LOW 21 /* Low bit for RD. */ 129 #define RA_LOW 16 /* Low bit for RA. */ 130 #define RB_LOW 11 /* Low bit for RB. */ 131 #define IMM_LOW 0 /* Low bit for immediate. */ 132 #define IMM_MBAR 21 /* low bit for mbar instruction. */ 133 #define IMM_WIDTH_LOW 6 /* Low bit for immediate width */ 134 135 #define RD_MASK 0x03E00000 136 #define RA_MASK 0x001F0000 137 #define RB_MASK 0x0000F800 138 #define IMM_MASK 0x0000FFFF 139 140 /* Imm mask for barrel shifts. */ 141 #define IMM5_MASK 0x0000001F 142 143 /* Imm mask for mbar. */ 144 #define IMM5_MBAR_MASK 0x03E00000 145 146 /* Imm mask for extract/insert width. */ 147 #define IMM5_WIDTH_MASK 0x000007C0 148 149 /* FSL imm mask for get, put instructions. */ 150 #define RFSL_MASK 0x000000F 151 152 /* Imm mask for msrset, msrclr instructions. */ 153 #define IMM15_MASK 0x00007FFF 154 155 #endif /* MICROBLAZE-OPCM */ 156