| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZMachineFunctionInfo.h | 69 void setVarArgsFirstGPR(Register GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 905 Register GPR = Copy->getOperand(1).getReg(); in ReplaceConstByVPNOTs() local
908 auto getImm = [&](Register GPR) -> unsigned { in ReplaceConstByVPNOTs()
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| /netbsd-src/bin/ed/ |
| H A D | ed.h | 64 #define GPR 002 /* print after command */ macro
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| /netbsd-src/sys/arch/sparc64/sparc64/ |
| H A D | emul.c | 51 #define GPR(tf, i) ((int32_t *)(u_long)&tf->tf_global)[i] macro
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| /netbsd-src/sys/arch/sparc/sparc/ |
| H A D | emul.c | 50 #define GPR(tf, i) ((int32_t *) &tf->tf_global)[i] macro
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| /netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/mips/ |
| H A D | mips16.S | 86 #define MERGE_GPRf(GPR, HIGH_FPR, LOW_FPR) \ argument
98 #define MERGE_GPRt(GPR, HIGH_FPR, LOW_FPR) \ argument
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| /netbsd-src/external/gpl3/gcc/dist/libgcc/config/mips/ |
| H A D | mips16.S | 86 #define MERGE_GPRf(GPR, HIGH_FPR, LOW_FPR) \ argument
98 #define MERGE_GPRt(GPR, HIGH_FPR, LOW_FPR) \ argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 428 RegisterSubReg GPR = MI->getOperand(i); in convertToPredForm() local
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| /netbsd-src/sys/arch/evbarm/stand/boot2440/ |
| H A D | dm9000.c | 89 #define GPR 0x1f /* gpio control */ macro
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| /netbsd-src/external/gpl3/gdb/dist/sim/ppc/ |
| H A D | registers.h | 333 #define GPR(N) cpu_registers(processor)->gpr[N] macro
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2216 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4228 static const MCPhysReg GPR[] = { in LowerFormalArguments_64SVR4() local
4696 static const MCPhysReg GPR[] = { in needStackSlotPassParameters() local
5930 static const MCPhysReg GPR[] = { in LowerCall_64SVR4() local
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | nid.h | 889 #define GPR(x) ((x) << 16) macro
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6952 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3500 Register GPR = TheMachineFunction.addLiveIn(Reg, &X86::GR64RegClass); in createVarArgAreaAndStoreRegisters() local
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