| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1296 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1298 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1300 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 392 Register FirstReg; in CreateRegs() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3365 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3382 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3436 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3501 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToFPR() local
4342 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
5284 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
5331 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandStoreDM1Macro() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 497 unsigned FirstReg = 0; in ScanInstruction() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 2258 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord()
2421 Register FirstReg, SecondReg; in RescheduleOps() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4319 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4372 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4519 unsigned FirstReg = 0; in HandleByVal() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1570 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3501 unsigned FirstReg; in tryParseVectorList() local
6157 unsigned FirstReg; in tryParseGPRSeqPair() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2265 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1632 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
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| H A D | PPCISelLowering.cpp | 6710 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 4754 unsigned FirstReg = Reg; in parseVectorList() local
|