1 /* $NetBSD: s3c2443.h,v 1.1.1.3 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 6 * 7 * Device Tree binding constants clock controllers of Samsung S3C2443 and later. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H 11 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H 12 13 /* 14 * Let each exported clock get a unique index, which is used on DT-enabled 15 * platforms to lookup the clock from a clock specifier. These indices are 16 * therefore considered an ABI and so must not be changed. This implies 17 * that new clocks should be added either in free spaces between clock groups 18 * or at the end. 19 */ 20 21 /* Core clocks. */ 22 #define MSYSCLK 1 23 #define ESYSCLK 2 24 #define ARMDIV 3 25 #define ARMCLK 4 26 #define HCLK 5 27 #define PCLK 6 28 #define MPLL 7 29 #define EPLL 8 30 31 /* Special clocks */ 32 #define SCLK_HSSPI0 16 33 #define SCLK_FIMD 17 34 #define SCLK_I2S0 18 35 #define SCLK_I2S1 19 36 #define SCLK_HSMMC1 20 37 #define SCLK_HSMMC_EXT 21 38 #define SCLK_CAM 22 39 #define SCLK_UART 23 40 #define SCLK_USBH 24 41 42 /* Muxes */ 43 #define MUX_HSSPI0 32 44 #define MUX_HSSPI1 33 45 #define MUX_HSMMC0 34 46 #define MUX_HSMMC1 35 47 48 /* hclk-gates */ 49 #define HCLK_DMA0 48 50 #define HCLK_DMA1 49 51 #define HCLK_DMA2 50 52 #define HCLK_DMA3 51 53 #define HCLK_DMA4 52 54 #define HCLK_DMA5 53 55 #define HCLK_DMA6 54 56 #define HCLK_DMA7 55 57 #define HCLK_CAM 56 58 #define HCLK_LCD 57 59 #define HCLK_USBH 58 60 #define HCLK_USBD 59 61 #define HCLK_IROM 60 62 #define HCLK_HSMMC0 61 63 #define HCLK_HSMMC1 62 64 #define HCLK_CFC 63 65 #define HCLK_SSMC 64 66 #define HCLK_DRAM 65 67 #define HCLK_2D 66 68 69 /* pclk-gates */ 70 #define PCLK_UART0 72 71 #define PCLK_UART1 73 72 #define PCLK_UART2 74 73 #define PCLK_UART3 75 74 #define PCLK_I2C0 76 75 #define PCLK_SDI 77 76 #define PCLK_SPI0 78 77 #define PCLK_ADC 79 78 #define PCLK_AC97 80 79 #define PCLK_I2S0 81 80 #define PCLK_PWM 82 81 #define PCLK_WDT 83 82 #define PCLK_RTC 84 83 #define PCLK_GPIO 85 84 #define PCLK_SPI1 86 85 #define PCLK_CHIPID 87 86 #define PCLK_I2C1 88 87 #define PCLK_I2S1 89 88 #define PCLK_PCM 90 89 90 /* Total number of clocks. */ 91 #define NR_CLKS (PCLK_PCM + 1) 92 93 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ 94