1 /* $NetBSD: bcm2835_dmac.h,v 1.5 2020/12/01 04:15:04 rin Exp $ */
2
3 /*-
4 * Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifndef BCM2835_DMAC_H
30 #define BCM2835_DMAC_H
31
32 #include <sys/endian.h>
33
34 #define DMAC_CS(n) (0x00 + (0x100 * (n)))
35 #define DMAC_CS_RESET __BIT(31)
36 #define DMAC_CS_ABORT __BIT(30)
37 #define DMAC_CS_DISDEBUG __BIT(29)
38 #define DMAC_CS_WAIT_FOR_OUTSTANDING_WRITES __BIT(28)
39 #define DMAC_CS_PANIC_PRIORITY __BITS(23,20)
40 #define DMAC_CS_PRIORITY __BITS(19,16)
41 #define DMAC_CS_ERROR __BIT(8)
42 #define DMAC_CS_WAITING_FOR_OUTSTANDING_WRITES __BIT(6)
43 #define DMAC_CS_DREQ_STOPS_DMA __BIT(5)
44 #define DMAC_CS_PAUSED __BIT(4)
45 #define DMAC_CS_DREQ __BIT(3)
46 #define DMAC_CS_INT __BIT(2)
47 #define DMAC_CS_END __BIT(1)
48 #define DMAC_CS_ACTIVE __BIT(0)
49 #define DMAC_CS_INTMASK (DMAC_CS_INT|DMAC_CS_END)
50 #define DMAC_CONBLK_AD(n) (0x04 + (0x100 * (n)))
51 #define DMAC_TI(n) (0x08 + (0x100 * (n)))
52 #define DMAC_SOURCE_AD(n) (0x0c + (0x100 * (n)))
53 #define DMAC_DEST_AD(n) (0x10 + (0x100 * (n)))
54 #define DMAC_TXFR_LEN(n) (0x14 + (0x100 * (n)))
55 #define DMAC_STRIDE(n) (0x18 + (0x100 * (n)))
56 #define DMAC_NEXTCONBK(n) (0x1c + (0x100 * (n)))
57 #define DMAC_DEBUG(n) (0x20 + (0x100 * (n)))
58 #define DMAC_DEBUG_LITE __BIT(28)
59 #define DMAC_DEBUG_VERSION __BITS(27,25)
60 #define DMAC_DEBUG_DMA_STATE __BITS(24,16)
61 #define DMAC_DEBUG_DMA_ID __BITS(15,8)
62 #define DMAC_DEBUG_OUTSTANDING_WRITES __BITS(7,4)
63 #define DMAC_DEBUG_READ_ERROR __BIT(2)
64 #define DMAC_DEBUG_FIFO_ERROR __BIT(1)
65 #define DMAC_DEBUG_READ_LAST_NOT_SET_ERROR __BIT(0)
66
67 /*
68 * Byte-order is little endain.
69 */
70 struct bcm_dmac_conblk {
71 uint32_t cb_ti;
72 #define DMAC_TI_NO_WIDE_BURSTS __BIT(26)
73 #define DMAC_TI_WAITS __BITS(25,21)
74 #define DMAC_TI_PERMAP __BITS(20,16)
75 #define DMAC_TI_BURST_LENGTH __BITS(15,12)
76 #define DMAC_TI_SRC_IGNORE __BIT(11)
77 #define DMAC_TI_SRC_DREQ __BIT(10)
78 #define DMAC_TI_SRC_WIDTH __BIT(9)
79 #define DMAC_TI_SRC_INC __BIT(8)
80 #define DMAC_TI_DEST_IGNORE __BIT(7)
81 #define DMAC_TI_DEST_DREQ __BIT(6)
82 #define DMAC_TI_DEST_WIDTH __BIT(5)
83 #define DMAC_TI_DEST_INC __BIT(4)
84 #define DMAC_TI_WAIT_RESP __BIT(3)
85 #define DMAC_TI_TDMODE __BIT(1)
86 #define DMAC_TI_INTEN __BIT(0)
87 uint32_t cb_source_ad;
88 uint32_t cb_dest_ad;
89 uint32_t cb_txfr_len;
90 #define DMAC_TXFR_LEN_YLENGTH __BITS(29,16)
91 #define DMAC_TXFR_LEN_XLENGTH __BITS(15,0)
92 uint32_t cb_stride;
93 #define DMAC_STRIDE_D_STRIDE __BITS(31,16)
94 #define DMAC_STRIDE_S_STRIDE __BITS(15,0)
95 uint32_t cb_nextconbk;
96 uint32_t cb_padding[2];
97 } __packed;
98
99 #define DMAC_INT_STATUS 0xfe0
100 #define DMAC_ENABLE 0xff0
101
102 enum bcm_dmac_type {
103 BCM_DMAC_TYPE_NORMAL,
104 BCM_DMAC_TYPE_LITE
105 };
106
107 struct bcm_dmac_channel;
108
109 struct bcm_dmac_channel *bcm_dmac_alloc(enum bcm_dmac_type, int,
110 void (*)(uint32_t, uint32_t, void *), void *);
111 void bcm_dmac_free(struct bcm_dmac_channel *);
112 void bcm_dmac_set_conblk_addr(struct bcm_dmac_channel *, bus_addr_t);
113 int bcm_dmac_transfer(struct bcm_dmac_channel *);
114 void bcm_dmac_halt(struct bcm_dmac_channel *);
115
116 static inline void
bcm_dmac_swap_conblk(struct bcm_dmac_conblk * conblk)117 bcm_dmac_swap_conblk(struct bcm_dmac_conblk *conblk)
118 {
119
120 HTOLE32(conblk->cb_ti);
121 HTOLE32(conblk->cb_source_ad);
122 HTOLE32(conblk->cb_dest_ad);
123 HTOLE32(conblk->cb_txfr_len);
124 HTOLE32(conblk->cb_stride);
125 HTOLE32(conblk->cb_nextconbk);
126 }
127
128 #endif /* !BCM2835_DMAC_H */
129