1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo2 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /* 8 * Copyright (C) 2000 - 2023, Intel Corp. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 */ 43 44 #include "acpi.h" 45 #include "accommon.h" 46 #include "acdisasm.h" 47 #include "actbinfo.h" 48 49 /* This module used for application-level code only */ 50 51 #define _COMPONENT ACPI_CA_DISASSEMBLER 52 ACPI_MODULE_NAME ("dmtbinfo2") 53 54 /* 55 * How to add a new table: 56 * 57 * - Add the C table definition to the actbl1.h or actbl2.h header. 58 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 59 * - Define the table in this file (for the disassembler). If any 60 * new data types are required (ACPI_DMT_*), see below. 61 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 62 * in acdisam.h 63 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 64 * If a simple table (with no subtables), no disassembly code is needed. 65 * Otherwise, create the AcpiDmDump* function for to disassemble the table 66 * and add it to the dmtbdump.c file. 67 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 68 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 69 * - Create a template for the new table 70 * - Add data table compiler support 71 * 72 * How to add a new data type (ACPI_DMT_*): 73 * 74 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 75 * - Add length and implementation cases in dmtable.c (disassembler) 76 * - Add type and length cases in dtutils.c (DT compiler) 77 */ 78 79 /* 80 * Remaining tables are not consumed directly by the ACPICA subsystem 81 */ 82 83 /******************************************************************************* 84 * 85 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface 86 * 87 * Conforms to "ACPI for Arm Components 1.1, Platform Design Document" 88 * ARM DEN0093 v1.1 89 * 90 ******************************************************************************/ 91 92 ACPI_DMTABLE_INFO AcpiDmTableInfoAgdi[] = 93 { 94 {ACPI_DMT_UINT8, ACPI_AGDI_OFFSET (Flags), "Flags (decoded below)", 0}, 95 {ACPI_DMT_FLAG0, ACPI_AGDI_FLAG_OFFSET (Flags, 0), "Signalling mode", 0}, 96 {ACPI_DMT_UINT24, ACPI_AGDI_OFFSET (Reserved[0]), "Reserved", 0}, 97 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (SdeiEvent), "SdeiEvent", 0}, 98 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (Gsiv), "Gsiv", 0}, 99 ACPI_DMT_TERMINATOR 100 }; 101 102 103 /******************************************************************************* 104 * 105 * APMT - ARM Performance Monitoring Unit Table 106 * 107 * Conforms to: 108 * ARM Performance Monitoring Unit Architecture 1.0 Platform Design Document 109 * ARM DEN0117 v1.0 November 25, 2021 110 * 111 ******************************************************************************/ 112 113 ACPI_DMTABLE_INFO AcpiDmTableInfoApmtNode[] = 114 { 115 {ACPI_DMT_UINT16, ACPI_APMTN_OFFSET (Length), "Length of APMT Node", 0}, 116 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Flags), "Node Flags", 0}, 117 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Dual Page Extension", 0}, 118 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Processor Affinity Type", 0}, 119 {ACPI_DMT_FLAG2, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "64-bit Atomic Support", 0}, 120 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Type), "Node Type", 0}, 121 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Id), "Unique Node Identifier", 0}, 122 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (InstPrimary), "Primary Node Instance", 0}, 123 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (InstSecondary), "Secondary Node Instance", 0}, 124 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress0), "Page 0 Base Address", 0}, 125 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress1), "Page 1 Base Address", 0}, 126 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrq), "Overflow Interrupt ID", 0}, 127 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Reserved), "Reserved", 0}, 128 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrqFlags), "Overflow Interrupt Flags", 0}, 129 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Mode", 0}, 130 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Type", 0}, 131 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ProcAffinity), "Processor Affinity", 0}, 132 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ImplId), "Implementation ID", 0}, 133 ACPI_DMT_TERMINATOR 134 }; 135 136 137 /******************************************************************************* 138 * 139 * IORT - IO Remapping Table 140 * 141 ******************************************************************************/ 142 143 ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] = 144 { 145 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0}, 146 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0}, 147 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0}, 148 ACPI_DMT_TERMINATOR 149 }; 150 151 /* Optional padding field */ 152 153 ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] = 154 { 155 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 156 ACPI_DMT_TERMINATOR 157 }; 158 159 /* Common Subtable header (one per Subtable) */ 160 161 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] = 162 { 163 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 164 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 165 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 166 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Reserved", 0}, 167 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 168 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 169 ACPI_DMT_TERMINATOR 170 }; 171 172 /* Common Subtable header (one per Subtable)- Revision 3 */ 173 174 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr3[] = 175 { 176 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 177 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 178 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 179 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Identifier", 0}, 180 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 181 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 182 ACPI_DMT_TERMINATOR 183 }; 184 185 ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] = 186 { 187 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL}, 188 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0}, 189 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0}, 190 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0}, 191 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0}, 192 {ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0}, 193 ACPI_DMT_TERMINATOR 194 }; 195 196 ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] = 197 { 198 {ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0}, 199 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0}, 200 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0}, 201 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0}, 202 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0}, 203 {ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0}, 204 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0}, 205 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0}, 206 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0}, 207 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0}, 208 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Ensured Coherency of Accesses", 0}, 209 ACPI_DMT_TERMINATOR 210 }; 211 212 /* IORT subtables */ 213 214 /* 0x00: ITS Group */ 215 216 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] = 217 { 218 {ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0}, 219 ACPI_DMT_TERMINATOR 220 }; 221 222 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] = 223 { 224 {ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL}, 225 ACPI_DMT_TERMINATOR 226 }; 227 228 /* 0x01: Named Component */ 229 230 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] = 231 { 232 {ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0}, 233 {ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0}, 234 {ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 235 {ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0}, 236 ACPI_DMT_TERMINATOR 237 }; 238 239 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] = 240 { 241 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 242 ACPI_DMT_TERMINATOR 243 }; 244 245 /* 0x02: PCI Root Complex */ 246 247 ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] = 248 { 249 {ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0}, 250 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0}, 251 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0}, 252 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 253 {ACPI_DMT_UINT16, ACPI_IORT2_OFFSET (PasidCapabilities), "PASID Capabilities", 0}, 254 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (Reserved[0]), "Reserved", 0}, 255 ACPI_DMT_TERMINATOR 256 }; 257 258 /* 0x03: SMMUv1/2 */ 259 260 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] = 261 { 262 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0}, 263 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0}, 264 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0}, 265 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0}, 266 {ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0}, 267 {ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0}, 268 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0}, 269 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0}, 270 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0}, 271 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0}, 272 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0}, 273 ACPI_DMT_TERMINATOR 274 }; 275 276 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] = 277 { 278 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0}, 279 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0}, 280 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0}, 281 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0}, 282 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0}, 283 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0}, 284 ACPI_DMT_TERMINATOR 285 }; 286 287 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] = 288 { 289 {ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL}, 290 ACPI_DMT_TERMINATOR 291 }; 292 293 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] = 294 { 295 {ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL}, 296 ACPI_DMT_TERMINATOR 297 }; 298 299 /* 0x04: SMMUv3 */ 300 301 ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] = 302 { 303 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0}, 304 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0}, 305 {ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0}, 306 {ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0}, 307 {ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0}, 308 {ACPI_DMT_FLAG4, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "DeviceID Valid", 0}, 309 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0}, 310 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0}, 311 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0}, 312 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0}, 313 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0}, 314 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0}, 315 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0}, 316 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0}, 317 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0}, 318 ACPI_DMT_TERMINATOR 319 }; 320 321 /* 0x05: PMCG */ 322 323 ACPI_DMTABLE_INFO AcpiDmTableInfoIort5[] = 324 { 325 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0}, 326 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (OverflowGsiv), "Overflow Interrupt GSIV", 0}, 327 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (NodeReference), "Node Reference", 0}, 328 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0}, 329 ACPI_DMT_TERMINATOR 330 }; 331 332 333 /* 0x06: RMR */ 334 335 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6[] = 336 { 337 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (Flags), "Flags (decoded below)", 0}, 338 {ACPI_DMT_FLAG0, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Remapping Permitted", 0}, 339 {ACPI_DMT_FLAG1, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Privileged", 0}, 340 {ACPI_DMT_FLAGS8_2, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Attributes", 0}, 341 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrCount), "Number of RMR Descriptors", 0}, 342 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrOffset), "RMR Descriptor Offset", 0}, 343 ACPI_DMT_TERMINATOR 344 }; 345 346 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6a[] = 347 { 348 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (BaseAddress), "Base Address of RMR", DT_OPTIONAL}, 349 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (Length), "Length of RMR", 0}, 350 {ACPI_DMT_UINT32, ACPI_IORT6A_OFFSET (Reserved), "Reserved", 0}, 351 ACPI_DMT_TERMINATOR 352 }; 353 354 /******************************************************************************* 355 * 356 * IVRS - I/O Virtualization Reporting Structure 357 * 358 ******************************************************************************/ 359 360 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] = 361 { 362 {ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0}, 363 {ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0}, 364 ACPI_DMT_TERMINATOR 365 }; 366 367 /* IVRS subtables */ 368 369 /* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */ 370 371 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware1[] = 372 { 373 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 374 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 375 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 376 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 377 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 378 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 379 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 380 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 381 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 382 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 383 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 384 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 385 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0}, 386 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0}, 387 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 388 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0}, 389 {ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (FeatureReporting), "Feature Reporting", 0}, 390 ACPI_DMT_TERMINATOR 391 }; 392 393 /* 0x11, 0x40: I/O Virtualization Hardware Definition (IVHD) Block */ 394 395 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware23[] = 396 { 397 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 398 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 399 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 400 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 401 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 402 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 403 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 404 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 405 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 406 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 407 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.Length), "Length", DT_LENGTH}, 408 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.DeviceId), "DeviceId", 0}, 409 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (CapabilityOffset), "Capability Offset", 0}, 410 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (BaseAddress), "Base Address", 0}, 411 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 412 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Info), "Virtualization Info", 0}, 413 {ACPI_DMT_UINT32, ACPI_IVRS01_OFFSET (Attributes), "Attributes", 0}, 414 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (EfrRegisterImage), "EFR Image", 0}, 415 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (Reserved), "Reserved", 0}, 416 ACPI_DMT_TERMINATOR 417 }; 418 419 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Device Entry Block */ 420 421 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsMemory[] = 422 { 423 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 424 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 425 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Unity", 0}, 426 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Readable", 0}, 427 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Writeable", 0}, 428 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Exclusion Range", 0}, 429 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 430 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 431 {ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0}, 432 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0}, 433 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0}, 434 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0}, 435 ACPI_DMT_TERMINATOR 436 }; 437 438 /* Device entry header for IVHD block */ 439 440 #define ACPI_DMT_IVRS_DE_HEADER \ 441 {ACPI_DMT_IVRS_DE, ACPI_IVRSD_OFFSET (Type), "Subtable Type", 0}, \ 442 {ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \ 443 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting (decoded below)", 0}, \ 444 {ACPI_DMT_FLAG0, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "INITPass", 0}, \ 445 {ACPI_DMT_FLAG1, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "EIntPass", 0}, \ 446 {ACPI_DMT_FLAG2, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "NMIPass", 0}, \ 447 {ACPI_DMT_FLAG3, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "Reserved", 0}, \ 448 {ACPI_DMT_FLAGS4, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "System MGMT", 0}, \ 449 {ACPI_DMT_FLAG6, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT0 Pass", 0}, \ 450 {ACPI_DMT_FLAG7, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT1 Pass", 0} 451 452 /* 4-byte device entry (Types 1,2,3,4) */ 453 454 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] = 455 { 456 ACPI_DMT_IVRS_DE_HEADER, 457 ACPI_DMT_TERMINATOR 458 }; 459 460 /* 8-byte device entry (Type Alias Select, Alias Start of Range) */ 461 462 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] = 463 { 464 ACPI_DMT_IVRS_DE_HEADER, 465 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0}, 466 {ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0}, 467 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0}, 468 ACPI_DMT_TERMINATOR 469 }; 470 471 /* 8-byte device entry (Type Extended Select, Extended Start of Range) */ 472 473 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] = 474 { 475 ACPI_DMT_IVRS_DE_HEADER, 476 {ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0}, 477 ACPI_DMT_TERMINATOR 478 }; 479 480 /* 8-byte device entry (Type Special Device) */ 481 482 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] = 483 { 484 ACPI_DMT_IVRS_DE_HEADER, 485 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0}, 486 {ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0}, 487 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0}, 488 ACPI_DMT_TERMINATOR 489 }; 490 491 /* Variable-length Device Entry Type 0xF0 */ 492 493 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHid[] = 494 { 495 ACPI_DMT_IVRS_DE_HEADER, 496 ACPI_DMT_TERMINATOR 497 }; 498 499 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidString[] = 500 { 501 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 502 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 503 {ACPI_DMT_IVRS_UNTERMINATED_STRING, 2, "UID", DT_OPTIONAL}, 504 ACPI_DMT_TERMINATOR 505 }; 506 507 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidInteger[] = 508 { 509 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 510 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 511 {ACPI_DMT_UINT64, 2, "UID", DT_OPTIONAL}, 512 ACPI_DMT_TERMINATOR 513 }; 514 515 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidString[] = 516 { 517 {ACPI_DMT_NAME8, 0, "ACPI HID", 0}, 518 ACPI_DMT_TERMINATOR 519 }; 520 521 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidInteger[] = 522 { 523 {ACPI_DMT_UINT64, 0, "ACPI HID", 0}, 524 ACPI_DMT_TERMINATOR 525 }; 526 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidString[] = 527 { 528 {ACPI_DMT_NAME8, 0, "ACPI CID", 0}, 529 ACPI_DMT_TERMINATOR 530 }; 531 532 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidInteger[] = 533 { 534 {ACPI_DMT_UINT64, 0, "ACPI CID", 0}, 535 ACPI_DMT_TERMINATOR 536 }; 537 538 539 /******************************************************************************* 540 * 541 * LPIT - Low Power Idle Table 542 * 543 ******************************************************************************/ 544 545 /* Main table consists only of the standard ACPI table header */ 546 547 /* Common Subtable header (one per Subtable) */ 548 549 ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] = 550 { 551 {ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0}, 552 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH}, 553 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0}, 554 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0}, 555 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 556 {ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0}, 557 {ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0}, 558 ACPI_DMT_TERMINATOR 559 }; 560 561 /* LPIT Subtables */ 562 563 /* 0: Native C-state */ 564 565 ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] = 566 { 567 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0}, 568 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0}, 569 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0}, 570 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0}, 571 {ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0}, 572 ACPI_DMT_TERMINATOR 573 }; 574 /******************************************************************************* 575 * 576 * MADT - Multiple APIC Description Table and subtables 577 * 578 ******************************************************************************/ 579 580 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] = 581 { 582 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0}, 583 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 584 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0}, 585 ACPI_DMT_TERMINATOR 586 }; 587 588 /* Common Subtable header (one per Subtable) */ 589 590 ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] = 591 { 592 {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0}, 593 {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH}, 594 ACPI_DMT_TERMINATOR 595 }; 596 597 /* MADT Subtables */ 598 599 /* 0: processor APIC */ 600 601 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] = 602 { 603 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0}, 604 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0}, 605 {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 606 {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 607 {ACPI_DMT_FLAG1, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Runtime Online Capable", 0}, 608 ACPI_DMT_TERMINATOR 609 }; 610 611 /* 1: IO APIC */ 612 613 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] = 614 { 615 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0}, 616 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0}, 617 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0}, 618 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0}, 619 ACPI_DMT_TERMINATOR 620 }; 621 622 /* 2: Interrupt Override */ 623 624 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] = 625 { 626 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0}, 627 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0}, 628 {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0}, 629 {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 630 {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 631 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 632 ACPI_DMT_TERMINATOR 633 }; 634 635 /* 3: NMI Sources */ 636 637 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] = 638 { 639 {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 640 {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 641 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 642 {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0}, 643 ACPI_DMT_TERMINATOR 644 }; 645 646 /* 4: Local APIC NMI */ 647 648 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] = 649 { 650 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0}, 651 {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 652 {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 653 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 654 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0}, 655 ACPI_DMT_TERMINATOR 656 }; 657 658 /* 5: Address Override */ 659 660 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] = 661 { 662 {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0}, 663 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0}, 664 ACPI_DMT_TERMINATOR 665 }; 666 667 /* 6: I/O Sapic */ 668 669 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] = 670 { 671 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0}, 672 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0}, 673 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 674 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0}, 675 ACPI_DMT_TERMINATOR 676 }; 677 678 /* 7: Local Sapic */ 679 680 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] = 681 { 682 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0}, 683 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0}, 684 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0}, 685 {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0}, 686 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 687 {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 688 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0}, 689 {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0}, 690 ACPI_DMT_TERMINATOR 691 }; 692 693 /* 8: Platform Interrupt Source */ 694 695 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] = 696 { 697 {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 698 {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 699 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 700 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0}, 701 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0}, 702 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0}, 703 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0}, 704 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0}, 705 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 706 {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0}, 707 ACPI_DMT_TERMINATOR 708 }; 709 710 /* 9: Processor Local X2_APIC (ACPI 4.0) */ 711 712 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] = 713 { 714 {ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0}, 715 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0}, 716 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 717 {ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 718 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0}, 719 ACPI_DMT_TERMINATOR 720 }; 721 722 /* 10: Local X2_APIC NMI (ACPI 4.0) */ 723 724 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] = 725 { 726 {ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 727 {ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 728 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 729 {ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0}, 730 {ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0}, 731 {ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0}, 732 ACPI_DMT_TERMINATOR 733 }; 734 735 /* 11: Generic Interrupt Controller (ACPI 5.0) */ 736 737 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] = 738 { 739 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 740 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 741 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 742 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 743 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 744 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 745 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 746 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 747 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 748 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 749 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 750 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 751 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 752 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 753 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 754 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 755 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 756 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 757 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 758 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 759 ACPI_DMT_TERMINATOR 760 }; 761 762 /* 11: Generic Interrupt Controller (ACPI 5.0) - MADT revision 6 */ 763 764 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11a[] = 765 { 766 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 767 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 768 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 769 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 770 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 771 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 772 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 773 {ACPI_DMT_FLAG3, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Online Capable", 0}, 774 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 775 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 776 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 777 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 778 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 779 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 780 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 781 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 782 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 783 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 784 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 785 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 786 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 787 ACPI_DMT_TERMINATOR 788 }; 789 790 /* 11: Generic Interrupt Controller (ACPI 5.0) - MADT revision 7 */ 791 792 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11b[] = 793 { 794 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 795 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 796 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 797 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 798 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 799 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 800 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 801 {ACPI_DMT_FLAG3, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Online Capable", 0}, 802 {ACPI_DMT_FLAG4, ACPI_MADT11_FLAG_OFFSET (Flags,0), "GICR non-coherent", 0}, 803 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 804 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 805 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 806 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 807 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 808 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 809 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 810 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 811 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 812 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 813 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 814 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 815 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 816 ACPI_DMT_TERMINATOR 817 }; 818 819 /* 12: Generic Interrupt Distributor (ACPI 5.0) */ 820 821 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] = 822 { 823 {ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0}, 824 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0}, 825 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0}, 826 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 827 {ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0}, 828 {ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0}, 829 ACPI_DMT_TERMINATOR 830 }; 831 832 /* 13: Generic MSI Frame (ACPI 5.1) */ 833 834 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] = 835 { 836 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0}, 837 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0}, 838 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0}, 839 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 840 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0}, 841 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0}, 842 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0}, 843 ACPI_DMT_TERMINATOR 844 }; 845 846 /* 14: Generic Redistributor (ACPI 5.1) */ 847 848 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] = 849 { 850 {ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 851 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 852 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 853 ACPI_DMT_TERMINATOR 854 }; 855 856 /* 14: Generic Redistributor (ACPI 5.1) */ 857 858 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14a[] = 859 { 860 {ACPI_DMT_UINT8, ACPI_MADT14_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 861 {ACPI_DMT_FLAG0, ACPI_MADT14_FLAG_OFFSET (Flags,0), "GICR non-coherent", 0}, 862 {ACPI_DMT_UINT8, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 863 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 864 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 865 ACPI_DMT_TERMINATOR 866 }; 867 868 /* 15: Generic Translator (ACPI 6.0) */ 869 870 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] = 871 { 872 {ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 873 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 874 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 875 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 876 ACPI_DMT_TERMINATOR 877 }; 878 879 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15a[] = 880 { 881 {ACPI_DMT_UINT8, ACPI_MADT15_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 882 {ACPI_DMT_FLAG0, ACPI_MADT15_FLAG_OFFSET (Flags,0), "GIC ITS non-coherent", 0}, 883 {ACPI_DMT_UINT8, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 884 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 885 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 886 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 887 ACPI_DMT_TERMINATOR 888 }; 889 890 /* 16: Multiprocessor wakeup structure (ACPI 6.4) */ 891 892 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt16[] = 893 { 894 {ACPI_DMT_UINT16, ACPI_MADT16_OFFSET (MailboxVersion), "Mailbox Version", 0}, 895 {ACPI_DMT_UINT32, ACPI_MADT16_OFFSET (Reserved), "Reserved", 0}, 896 {ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (BaseAddress), "Mailbox Address", 0}, 897 ACPI_DMT_TERMINATOR 898 }; 899 900 /* 17: core interrupt controller */ 901 902 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt17[] = 903 { 904 {ACPI_DMT_UINT8, ACPI_MADT17_OFFSET (Version), "Version", 0}, 905 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (ProcessorId), "ProcessorId", 0}, 906 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (CoreId), "CoreId", 0}, 907 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (Flags), "Flags", 0}, 908 ACPI_DMT_TERMINATOR 909 }; 910 911 /* 18: Legacy I/O interrupt controller */ 912 913 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt18[] = 914 { 915 {ACPI_DMT_UINT8, ACPI_MADT18_OFFSET (Version), "Version", 0}, 916 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (Address), "Address", 0}, 917 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Size), "Size", 0}, 918 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Cascade), "Cascade", 0}, 919 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (CascadeMap), "CascadeMap", 0}, 920 ACPI_DMT_TERMINATOR 921 }; 922 923 /* 19: HT interrupt controller */ 924 925 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt19[] = 926 { 927 {ACPI_DMT_UINT8, ACPI_MADT19_OFFSET (Version), "Version", 0}, 928 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Address), "Address", 0}, 929 {ACPI_DMT_UINT16, ACPI_MADT19_OFFSET (Size), "Size", 0}, 930 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Cascade), "Cascade", 0}, 931 ACPI_DMT_TERMINATOR 932 }; 933 934 /* 20: Extend I/O interrupt controller */ 935 936 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt20[] = 937 { 938 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Version), "Version", 0}, 939 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Cascade), "Cascade", 0}, 940 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Node), "Node", 0}, 941 {ACPI_DMT_UINT64, ACPI_MADT20_OFFSET (NodeMap), "NodeMap", 0}, 942 ACPI_DMT_TERMINATOR 943 }; 944 945 /* 21: MSI controller */ 946 947 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt21[] = 948 { 949 {ACPI_DMT_UINT8, ACPI_MADT21_OFFSET (Version), "Version", 0}, 950 {ACPI_DMT_UINT64, ACPI_MADT21_OFFSET (MsgAddress), "MsgAddress", 0}, 951 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Start), "Start", 0}, 952 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Count), "Count", 0}, 953 ACPI_DMT_TERMINATOR 954 }; 955 956 /* 22: BIO interrupt controller */ 957 958 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt22[] = 959 { 960 {ACPI_DMT_UINT8, ACPI_MADT22_OFFSET (Version), "Version", 0}, 961 {ACPI_DMT_UINT64, ACPI_MADT22_OFFSET (Address), "Address", 0}, 962 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Size), "Size", 0}, 963 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Id), "Id", 0}, 964 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (GsiBase), "GsiBase", 0}, 965 ACPI_DMT_TERMINATOR 966 }; 967 968 /* 23: LPC interrupt controller */ 969 970 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt23[] = 971 { 972 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Version), "Version", 0}, 973 {ACPI_DMT_UINT64, ACPI_MADT23_OFFSET (Address), "Address", 0}, 974 {ACPI_DMT_UINT16, ACPI_MADT23_OFFSET (Size), "Size", 0}, 975 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Cascade), "Cascade", 0}, 976 ACPI_DMT_TERMINATOR 977 }; 978 979 /* 24: RINTC interrupt controller */ 980 981 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt24[] = 982 { 983 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Version), "Version", 0}, 984 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Reserved), "Reserved", 0}, 985 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Flags), "Flags", 0}, 986 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (HartId), "HartId", 0}, 987 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Uid), "Uid", 0}, 988 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ExtIntcId), "ExtIntcId", 0}, 989 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (ImsicAddr), "ImsicAddr", 0}, 990 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ImsicSize), "ImsicSize", 0}, 991 ACPI_DMT_TERMINATOR 992 }; 993 994 /* 25: RISC-V IMSIC interrupt controller */ 995 996 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt25[] = 997 { 998 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Version), "Version", 0}, 999 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Reserved), "Reserved", 0}, 1000 {ACPI_DMT_UINT32, ACPI_MADT25_OFFSET (Flags), "Flags", 0}, 1001 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumIds), "NumIds", 0}, 1002 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumGuestIds), "NumGuestIds", 0}, 1003 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GuestIndexBits), "GuestIndexBits", 0}, 1004 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (HartIndexBits), "HartIndexBits", 0}, 1005 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexBits), "GroupIndexBits", 0}, 1006 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexShift), "GroupIndexShift", 0}, 1007 ACPI_DMT_TERMINATOR 1008 }; 1009 1010 /* 26: RISC-V APLIC interrupt controller */ 1011 1012 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt26[] = 1013 { 1014 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Version), "Version", 0}, 1015 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Id), "Id", 0}, 1016 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Flags), "Flags", 0}, 1017 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (HwId), "HwId", 0}, 1018 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumIdcs), "NumIdcs", 0}, 1019 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumSources), "NumSources", 0}, 1020 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (GsiBase), "GsiBase", 0}, 1021 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (BaseAddr), "BaseAddr", 0}, 1022 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Size), "Size", 0}, 1023 ACPI_DMT_TERMINATOR 1024 }; 1025 1026 /* 27: RISC-V PLIC interrupt controller */ 1027 1028 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt27[] = 1029 { 1030 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Version), "Version", 0}, 1031 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Id), "Id", 0}, 1032 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (HwId), "HwId", 0}, 1033 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (NumIrqs), "NumIrqs", 0}, 1034 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (MaxPrio), "MaxPrio", 0}, 1035 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Flags), "Flags", 0}, 1036 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Size), "Size", 0}, 1037 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (BaseAddr), "BaseAddr", 0}, 1038 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (GsiBase), "GsiBase", 0}, 1039 ACPI_DMT_TERMINATOR 1040 }; 1041 1042 /* 128: OEM data structure */ 1043 1044 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt128[] = 1045 { 1046 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", 0}, 1047 ACPI_DMT_TERMINATOR 1048 }; 1049 1050 /******************************************************************************* 1051 * 1052 * MCFG - PCI Memory Mapped Configuration table and Subtable 1053 * 1054 ******************************************************************************/ 1055 1056 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] = 1057 { 1058 {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved", 0}, 1059 ACPI_DMT_TERMINATOR 1060 }; 1061 1062 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] = 1063 { 1064 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0}, 1065 {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number", 0}, 1066 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number", 0}, 1067 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number", 0}, 1068 {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved", 0}, 1069 ACPI_DMT_TERMINATOR 1070 }; 1071 1072 1073 /******************************************************************************* 1074 * 1075 * MCHI - Management Controller Host Interface table 1076 * 1077 ******************************************************************************/ 1078 1079 ACPI_DMTABLE_INFO AcpiDmTableInfoMchi[] = 1080 { 1081 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterfaceType), "Interface Type", 0}, 1082 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Protocol), "Protocol", 0}, 1083 {ACPI_DMT_UINT64, ACPI_MCHI_OFFSET (ProtocolData), "Protocol Data", 0}, 1084 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterruptType), "Interrupt Type", 0}, 1085 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Gpe), "Gpe", 0}, 1086 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDeviceFlag), "Pci Device Flag", 0}, 1087 {ACPI_DMT_UINT32, ACPI_MCHI_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 1088 {ACPI_DMT_GAS, ACPI_MCHI_OFFSET (ControlRegister), "Control Register", 0}, 1089 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciSegment), "Pci Segment", 0}, 1090 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciBus), "Pci Bus", 0}, 1091 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDevice), "Pci Device", 0}, 1092 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciFunction), "Pci Function", 0}, 1093 ACPI_DMT_TERMINATOR 1094 }; 1095 1096 /******************************************************************************* 1097 * 1098 * MPAM - Memory System Resource Partitioning and Monitoring Tables 1099 * Arm's DEN0065 MPAM ACPI 2.0. December 2022. 1100 ******************************************************************************/ 1101 1102 /* MPAM subtables */ 1103 1104 /* 0: MPAM Resource Node Structure - A root MSC table. 1105 * Arm's DEN0065 MPAM ACPI 2.0. Table 4: MPAM MSC node body. 1106 */ 1107 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam0[] = 1108 { 1109 {ACPI_DMT_UINT16, ACPI_MPAM0_OFFSET (Length), "Length", 0}, 1110 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (InterfaceType), "Interface type", 0}, 1111 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (Reserved), "Reserved", 0}, 1112 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Identifier), "Identifier", 0}, 1113 {ACPI_DMT_UINT64, ACPI_MPAM0_OFFSET (BaseAddress), "Base address", 0}, 1114 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MMIOSize), "MMIO size", 0}, 1115 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterrupt), "Overflow interrupt", 0}, 1116 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptFlags), "Overflow interrupt flags", 0}, 1117 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved1), "Reserved1", 0}, 1118 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptAffinity), "Overflow interrupt affinity", 0}, 1119 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterrupt), "Error interrupt", 0}, 1120 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptFlags), "Error interrupt flags", 0}, 1121 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved2), "Reserved2", 0}, 1122 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptAffinity), "Error interrupt affinity", 0}, 1123 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MaxNrdyUsec), "MAX_NRDY_USEC", 0}, 1124 {ACPI_DMT_NAME8, ACPI_MPAM0_OFFSET (HardwareIdLinkedDevice), "Hardware ID of linked device", 0}, 1125 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (InstanceIdLinkedDevice), "Instance ID of linked device", 0}, 1126 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (NumResourceNodes), "Number of resource nodes", 0}, 1127 1128 ACPI_DMT_TERMINATOR 1129 }; 1130 1131 /* 1: MPAM Resource (RIS) Node Structure - A subtable of MSC Nodes. 1132 * Arm's DEN0065 MPAM ACPI 2.0. Table 9: Resource node. 1133 */ 1134 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1[] = 1135 { 1136 {ACPI_DMT_UINT32, ACPI_MPAM1_OFFSET (Identifier), "Identifier", 0}, 1137 {ACPI_DMT_UINT8, ACPI_MPAM1_OFFSET (RISIndex), "RIS Index", 0}, 1138 {ACPI_DMT_UINT16, ACPI_MPAM1_OFFSET (Reserved1), "Reserved1", 0}, 1139 {ACPI_DMT_MPAM_LOCATOR, ACPI_MPAM1_OFFSET (LocatorType), "Locator type", 0}, 1140 ACPI_DMT_TERMINATOR 1141 }; 1142 1143 /* An RIS field part of the RIS subtable */ 1144 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1Deps[] = 1145 { 1146 {ACPI_DMT_UINT32, 0, "Number of functional dependencies", 0}, 1147 ACPI_DMT_TERMINATOR 1148 }; 1149 1150 /* 1A: MPAM Processor cache locator descriptor. A subtable of RIS. 1151 * Arm's DEN0065 MPAM ACPI 2.0. Table 13. 1152 */ 1153 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1A[] = 1154 { 1155 {ACPI_DMT_UINT64, ACPI_MPAM1A_OFFSET (CacheReference), "Cache reference", 0}, 1156 {ACPI_DMT_UINT32, ACPI_MPAM1A_OFFSET (Reserved), "Reserved", 0}, 1157 ACPI_DMT_TERMINATOR 1158 }; 1159 1160 /* 1B: MPAM Memory locator descriptor. A subtable of RIS. 1161 * Arm's DEN0065 MPAM ACPI 2.0. Table 14. 1162 */ 1163 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1B[] = 1164 { 1165 {ACPI_DMT_UINT64, ACPI_MPAM1B_OFFSET (ProximityDomain), "Proximity domain", 0}, 1166 {ACPI_DMT_UINT32, ACPI_MPAM1B_OFFSET (Reserved), "Reserved", 0}, 1167 ACPI_DMT_TERMINATOR 1168 }; 1169 1170 /* 1C: MPAM SMMU locator descriptor. A subtable of RIS. 1171 * Arm's DEN0065 MPAM ACPI 2.0. Table 15. 1172 */ 1173 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1C[] = 1174 { 1175 {ACPI_DMT_UINT64, ACPI_MPAM1C_OFFSET (SmmuInterface), "SMMU Interface", 0}, 1176 {ACPI_DMT_UINT32, ACPI_MPAM1C_OFFSET (Reserved), "Reserved", 0}, 1177 ACPI_DMT_TERMINATOR 1178 }; 1179 1180 /* 1D: MPAM Memory-side cache locator descriptor. A subtable of RIS. 1181 * Arm's DEN0065 MPAM ACPI 2.0. Table 16. 1182 */ 1183 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1D[] = 1184 { 1185 {ACPI_DMT_UINT56, ACPI_MPAM1D_OFFSET (Reserved), "Reserved", 0}, 1186 {ACPI_DMT_UINT8, ACPI_MPAM1D_OFFSET (Level), "Level", 0}, 1187 {ACPI_DMT_UINT32, ACPI_MPAM1D_OFFSET (Reference), "Reference", 0}, 1188 ACPI_DMT_TERMINATOR 1189 }; 1190 1191 /* 1E: MPAM ACPI device locator descriptor. A subtable of RIS. 1192 * Arm's DEN0065 MPAM ACPI 2.0. Table 17. 1193 */ 1194 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1E[] = 1195 { 1196 {ACPI_DMT_UINT64, ACPI_MPAM1E_OFFSET (AcpiHwId), "ACPI Hardware ID", 0}, 1197 {ACPI_DMT_UINT32, ACPI_MPAM1E_OFFSET (AcpiUniqueId), "ACPI Unique ID", 0}, 1198 ACPI_DMT_TERMINATOR 1199 }; 1200 1201 /* 1F: MPAM Interconnect locator descriptor. A subtable of RIS. 1202 * Arm's DEN0065 MPAM ACPI 2.0. Table 18. 1203 */ 1204 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1F[] = 1205 { 1206 {ACPI_DMT_UINT64, ACPI_MPAM1F_OFFSET (InterConnectDescTblOff), "Interconnect descriptor table offset", 0}, 1207 {ACPI_DMT_UINT32, ACPI_MPAM1F_OFFSET (Reserved), "Reserved", 0}, 1208 ACPI_DMT_TERMINATOR 1209 }; 1210 1211 /* 1G: MPAM Locator structure. 1212 * Arm's DEN0065 MPAM ACPI 2.0. Table 12. 1213 */ 1214 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1G[] = 1215 { 1216 {ACPI_DMT_UINT64, ACPI_MPAM1G_OFFSET (Descriptor1), "Descriptor1", 0}, 1217 {ACPI_DMT_UINT32, ACPI_MPAM1G_OFFSET (Descriptor2), "Descriptor2", 0}, 1218 ACPI_DMT_TERMINATOR 1219 }; 1220 1221 /* 2: MPAM Functional dependency descriptor. 1222 * Arm's DEN0065 MPAM ACPI 2.0. Table 10. 1223 */ 1224 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam2[] = 1225 { 1226 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Producer), "Producer", 0}, 1227 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Reserved), "Reserved", 0}, 1228 ACPI_DMT_TERMINATOR 1229 }; 1230 1231 1232 /******************************************************************************* 1233 * 1234 * MPST - Memory Power State Table 1235 * 1236 ******************************************************************************/ 1237 1238 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst[] = 1239 { 1240 {ACPI_DMT_UINT8, ACPI_MPST_OFFSET (ChannelId), "Channel ID", 0}, 1241 {ACPI_DMT_UINT24, ACPI_MPST_OFFSET (Reserved1[0]), "Reserved", 0}, 1242 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (PowerNodeCount), "Power Node Count", 0}, 1243 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (Reserved2), "Reserved", 0}, 1244 ACPI_DMT_TERMINATOR 1245 }; 1246 1247 /* MPST subtables */ 1248 1249 /* 0: Memory Power Node Structure */ 1250 1251 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0[] = 1252 { 1253 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1254 {ACPI_DMT_FLAG0, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Node Enabled", 0}, 1255 {ACPI_DMT_FLAG1, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Power Managed", 0}, 1256 {ACPI_DMT_FLAG2, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Hot Plug Capable", 0}, 1257 1258 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Reserved1), "Reserved", 0}, 1259 {ACPI_DMT_UINT16, ACPI_MPST0_OFFSET (NodeId), "Node ID", 0}, 1260 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (Length), "Length", 0}, 1261 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0}, 1262 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeLength), "Range Length", 0}, 1263 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPowerStates), "Num Power States", 0}, 1264 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPhysicalComponents), "Num Physical Components", 0}, 1265 ACPI_DMT_TERMINATOR 1266 }; 1267 1268 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */ 1269 1270 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0A[] = 1271 { 1272 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (PowerState), "Power State", 0}, 1273 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (InfoIndex), "InfoIndex", 0}, 1274 ACPI_DMT_TERMINATOR 1275 }; 1276 1277 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */ 1278 1279 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0B[] = 1280 { 1281 {ACPI_DMT_UINT16, ACPI_MPST0B_OFFSET (ComponentId), "Component Id", 0}, 1282 ACPI_DMT_TERMINATOR 1283 }; 1284 1285 /* 01: Power Characteristics Count (follows all Power Node(s) above) */ 1286 1287 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[] = 1288 { 1289 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (CharacteristicsCount), "Characteristics Count", 0}, 1290 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (Reserved), "Reserved", 0}, 1291 ACPI_DMT_TERMINATOR 1292 }; 1293 1294 /* 02: Memory Power State Characteristics Structure */ 1295 1296 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[] = 1297 { 1298 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (StructureId), "Structure ID", 0}, 1299 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1300 {ACPI_DMT_FLAG0, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Memory Preserved", 0}, 1301 {ACPI_DMT_FLAG1, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Entry", 0}, 1302 {ACPI_DMT_FLAG2, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Exit", 0}, 1303 1304 {ACPI_DMT_UINT16, ACPI_MPST2_OFFSET (Reserved1), "Reserved", 0}, 1305 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (AveragePower), "Average Power", 0}, 1306 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (PowerSaving), "Power Saving", 0}, 1307 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0}, 1308 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (Reserved2), "Reserved", 0}, 1309 ACPI_DMT_TERMINATOR 1310 }; 1311 1312 1313 /******************************************************************************* 1314 * 1315 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 1316 * 1317 ******************************************************************************/ 1318 1319 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[] = 1320 { 1321 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (ProximityOffset), "Proximity Offset", 0}, 1322 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxProximityDomains), "Max Proximity Domains", 0}, 1323 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxClockDomains), "Max Clock Domains", 0}, 1324 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0}, 1325 ACPI_DMT_TERMINATOR 1326 }; 1327 1328 /* Subtable - Maximum Proximity Domain Information. Version 1 */ 1329 1330 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] = 1331 { 1332 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Revision), "Revision", 0}, 1333 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Length), "Length", DT_LENGTH}, 1334 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeStart), "Domain Range Start", 0}, 1335 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeEnd), "Domain Range End", 0}, 1336 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (ProcessorCapacity), "Processor Capacity", 0}, 1337 {ACPI_DMT_UINT64, ACPI_MSCT0_OFFSET (MemoryCapacity), "Memory Capacity", 0}, 1338 ACPI_DMT_TERMINATOR 1339 }; 1340 1341 1342 /******************************************************************************* 1343 * 1344 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0) 1345 * 1346 ******************************************************************************/ 1347 1348 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit[] = 1349 { 1350 {ACPI_DMT_UINT32, ACPI_NFIT_OFFSET (Reserved), "Reserved", 0}, 1351 ACPI_DMT_TERMINATOR 1352 }; 1353 1354 /* Common Subtable header */ 1355 1356 ACPI_DMTABLE_INFO AcpiDmTableInfoNfitHdr[] = 1357 { 1358 {ACPI_DMT_NFIT, ACPI_NFITH_OFFSET (Type), "Subtable Type", 0}, 1359 {ACPI_DMT_UINT16, ACPI_NFITH_OFFSET (Length), "Length", DT_LENGTH}, 1360 ACPI_DMT_TERMINATOR 1361 }; 1362 1363 /* 0: System Physical Address Range Structure */ 1364 1365 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit0[] = 1366 { 1367 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (RangeIndex), "Range Index", 0}, 1368 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1369 {ACPI_DMT_FLAG0, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Add/Online Operation Only", 0}, 1370 {ACPI_DMT_FLAG1, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 1371 {ACPI_DMT_FLAG2, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Location Cookie Valid", 0}, 1372 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (Reserved), "Reserved", 0}, 1373 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 1374 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Region Type GUID", 0}, 1375 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0}, 1376 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0}, 1377 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (MemoryMapping), "Memory Map Attribute", 0}, 1378 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (LocationCookie), "Location Cookie", 0}, /* ACPI 6.4 */ 1379 ACPI_DMT_TERMINATOR 1380 }; 1381 1382 /* 1: Memory Device to System Address Range Map Structure */ 1383 1384 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit1[] = 1385 { 1386 {ACPI_DMT_UINT32, ACPI_NFIT1_OFFSET (DeviceHandle), "Device Handle", 0}, 1387 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (PhysicalId), "Physical Id", 0}, 1388 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionId), "Region Id", 0}, 1389 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RangeIndex), "Range Index", 0}, 1390 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionIndex), "Control Region Index", 0}, 1391 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionSize), "Region Size", 0}, 1392 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionOffset), "Region Offset", 0}, 1393 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0}, 1394 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1395 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveWays), "Interleave Ways", 0}, 1396 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Flags), "Flags", DT_FLAG}, 1397 {ACPI_DMT_FLAG0, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Save to device failed", 0}, 1398 {ACPI_DMT_FLAG1, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Restore from device failed", 0}, 1399 {ACPI_DMT_FLAG2, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Platform flush failed", 0}, 1400 {ACPI_DMT_FLAG3, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Device not armed", 0}, 1401 {ACPI_DMT_FLAG4, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events observed", 0}, 1402 {ACPI_DMT_FLAG5, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events enabled", 0}, 1403 {ACPI_DMT_FLAG6, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Mapping failed", 0}, 1404 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Reserved), "Reserved", 0}, 1405 ACPI_DMT_TERMINATOR 1406 }; 1407 1408 /* 2: Interleave Structure */ 1409 1410 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2[] = 1411 { 1412 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1413 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (Reserved), "Reserved", 0}, 1414 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineCount), "Line Count", 0}, 1415 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineSize), "Line Size", 0}, 1416 ACPI_DMT_TERMINATOR 1417 }; 1418 1419 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2a[] = 1420 { 1421 {ACPI_DMT_UINT32, 0, "Line Offset", DT_OPTIONAL}, 1422 ACPI_DMT_TERMINATOR 1423 }; 1424 1425 /* 3: SMBIOS Management Information Structure */ 1426 1427 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3[] = 1428 { 1429 {ACPI_DMT_UINT32, ACPI_NFIT3_OFFSET (Reserved), "Reserved", 0}, 1430 ACPI_DMT_TERMINATOR 1431 }; 1432 1433 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3a[] = 1434 { 1435 {ACPI_DMT_RAW_BUFFER, 0, "SMBIOS Table Entries", DT_OPTIONAL}, 1436 ACPI_DMT_TERMINATOR 1437 }; 1438 1439 /* 4: NVDIMM Control Region Structure */ 1440 1441 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit4[] = 1442 { 1443 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RegionIndex), "Region Index", 0}, 1444 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (VendorId), "Vendor Id", 0}, 1445 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (DeviceId), "Device Id", 0}, 1446 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RevisionId), "Revision Id", 0}, 1447 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemVendorId), "Subsystem Vendor Id", 0}, 1448 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemDeviceId), "Subsystem Device Id", 0}, 1449 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemRevisionId), "Subsystem Revision Id", 0}, 1450 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ValidFields), "Valid Fields", 0}, 1451 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ManufacturingLocation), "Manufacturing Location", 0}, 1452 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (ManufacturingDate), "Manufacturing Date", 0}, 1453 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Reserved[0]), "Reserved", 0}, 1454 {ACPI_DMT_UINT32, ACPI_NFIT4_OFFSET (SerialNumber), "Serial Number", 0}, 1455 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Code), "Code", 0}, 1456 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Windows), "Window Count", 0}, 1457 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (WindowSize), "Window Size", 0}, 1458 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandOffset), "Command Offset", 0}, 1459 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandSize), "Command Size", 0}, 1460 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusOffset), "Status Offset", 0}, 1461 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusSize), "Status Size", 0}, 1462 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Flags), "Flags", DT_FLAG}, 1463 {ACPI_DMT_FLAG0, ACPI_NFIT4_FLAG_OFFSET (Flags,0), "Windows buffered", 0}, 1464 {ACPI_DMT_UINT48, ACPI_NFIT4_OFFSET (Reserved1[0]), "Reserved1", 0}, 1465 ACPI_DMT_TERMINATOR 1466 }; 1467 1468 /* 5: NVDIMM Block Data Window Region Structure */ 1469 1470 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit5[] = 1471 { 1472 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (RegionIndex), "Region Index", 0}, 1473 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (Windows), "Window Count", 0}, 1474 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Offset), "Offset", 0}, 1475 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Size), "Size", 0}, 1476 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Capacity), "Capacity", 0}, 1477 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0}, 1478 ACPI_DMT_TERMINATOR 1479 }; 1480 1481 /* 6: Flush Hint Address Structure */ 1482 1483 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6[] = 1484 { 1485 {ACPI_DMT_UINT32, ACPI_NFIT6_OFFSET (DeviceHandle), "Device Handle", 0}, 1486 {ACPI_DMT_UINT16, ACPI_NFIT6_OFFSET (HintCount), "Hint Count", 0}, 1487 {ACPI_DMT_UINT48, ACPI_NFIT6_OFFSET (Reserved[0]), "Reserved", 0}, 1488 ACPI_DMT_TERMINATOR 1489 }; 1490 1491 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6a[] = 1492 { 1493 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL}, 1494 ACPI_DMT_TERMINATOR 1495 }; 1496 1497 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit7[] = 1498 { 1499 {ACPI_DMT_UINT8, ACPI_NFIT7_OFFSET (HighestCapability), "Highest Capability", 0}, 1500 {ACPI_DMT_UINT24, ACPI_NFIT7_OFFSET (Reserved[0]), "Reserved", 0}, 1501 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Capabilities), "Capabilities (decoded below)", DT_FLAG}, 1502 {ACPI_DMT_FLAG0, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Cache Flush to NVDIMM", 0}, 1503 {ACPI_DMT_FLAG1, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Flush to NVDIMM", 0}, 1504 {ACPI_DMT_FLAG2, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Mirroring", 0}, 1505 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Reserved2), "Reserved", 0}, 1506 ACPI_DMT_TERMINATOR 1507 }; 1508 1509 1510 /******************************************************************************* 1511 * 1512 * PCCT - Platform Communications Channel Table (ACPI 5.0) 1513 * 1514 ******************************************************************************/ 1515 1516 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct[] = 1517 { 1518 {ACPI_DMT_UINT32, ACPI_PCCT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1519 {ACPI_DMT_FLAG0, ACPI_PCCT_FLAG_OFFSET (Flags,0), "Platform", 0}, 1520 {ACPI_DMT_UINT64, ACPI_PCCT_OFFSET (Reserved), "Reserved", 0}, 1521 ACPI_DMT_TERMINATOR 1522 }; 1523 1524 /* PCCT subtables */ 1525 1526 ACPI_DMTABLE_INFO AcpiDmTableInfoPcctHdr[] = 1527 { 1528 {ACPI_DMT_PCCT, ACPI_PCCT0_OFFSET (Header.Type), "Subtable Type", 0}, 1529 {ACPI_DMT_UINT8, ACPI_PCCT0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1530 ACPI_DMT_TERMINATOR 1531 }; 1532 1533 /* 0: Generic Communications Subspace */ 1534 1535 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct0[] = 1536 { 1537 {ACPI_DMT_UINT48, ACPI_PCCT0_OFFSET (Reserved[0]), "Reserved", 0}, 1538 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0}, 1539 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0}, 1540 {ACPI_DMT_GAS, ACPI_PCCT0_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1541 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (PreserveMask), "Preserve Mask", 0}, 1542 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (WriteMask), "Write Mask", 0}, 1543 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0}, 1544 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1545 {ACPI_DMT_UINT16, ACPI_PCCT0_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1546 ACPI_DMT_TERMINATOR 1547 }; 1548 1549 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 1550 1551 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct1[] = 1552 { 1553 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1554 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1555 {ACPI_DMT_FLAG0, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1556 {ACPI_DMT_FLAG1, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Mode", 0}, 1557 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Reserved), "Reserved", 0}, 1558 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0}, 1559 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0}, 1560 {ACPI_DMT_GAS, ACPI_PCCT1_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1561 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (PreserveMask), "Preserve Mask", 0}, 1562 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (WriteMask), "Write Mask", 0}, 1563 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0}, 1564 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1565 {ACPI_DMT_UINT16, ACPI_PCCT1_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1566 ACPI_DMT_TERMINATOR 1567 }; 1568 1569 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 1570 1571 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct2[] = 1572 { 1573 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1574 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1575 {ACPI_DMT_FLAG0, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1576 {ACPI_DMT_FLAG1, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Mode", 0}, 1577 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Reserved), "Reserved", 0}, 1578 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0}, 1579 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0}, 1580 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1581 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (PreserveMask), "Preserve Mask", 0}, 1582 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (WriteMask), "Write Mask", 0}, 1583 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0}, 1584 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1585 {ACPI_DMT_UINT16, ACPI_PCCT2_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1586 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1587 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1588 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckWriteMask), "ACK Write Mask", 0}, 1589 ACPI_DMT_TERMINATOR 1590 }; 1591 1592 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 1593 1594 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct3[] = 1595 { 1596 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1597 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1598 {ACPI_DMT_FLAG0, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1599 {ACPI_DMT_FLAG1, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Mode", 0}, 1600 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Reserved1), "Reserved", 0}, 1601 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0}, 1602 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0}, 1603 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1604 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (PreserveMask), "Preserve Mask", 0}, 1605 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (WriteMask), "Write Mask", 0}, 1606 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0}, 1607 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1608 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1609 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1610 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1611 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1612 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (Reserved2), "Reserved", 0}, 1613 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1614 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1615 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1616 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1617 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1618 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1619 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1620 ACPI_DMT_TERMINATOR 1621 }; 1622 1623 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 1624 1625 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct4[] = 1626 { 1627 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1628 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1629 {ACPI_DMT_FLAG0, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1630 {ACPI_DMT_FLAG1, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Mode", 0}, 1631 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Reserved1), "Reserved", 0}, 1632 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0}, 1633 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0}, 1634 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1635 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (PreserveMask), "Preserve Mask", 0}, 1636 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (WriteMask), "Write Mask", 0}, 1637 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Latency), "Command Latency", 0}, 1638 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1639 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1640 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1641 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1642 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1643 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (Reserved2), "Reserved", 0}, 1644 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1645 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1646 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1647 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1648 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1649 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1650 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1651 ACPI_DMT_TERMINATOR 1652 }; 1653 1654 /* 5: HW Registers based Communications Subspace */ 1655 1656 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct5[] = 1657 { 1658 {ACPI_DMT_UINT16, ACPI_PCCT5_OFFSET (Version), "Version", 0}, 1659 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (BaseAddress), "Base Address", 0}, 1660 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (Length), "Length", 0}, 1661 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1662 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellPreserve), "Preserve Mask", 0}, 1663 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellWrite), "Write Mask", 0}, 1664 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1665 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1666 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1667 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1668 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (NominalLatency), "Nominal Latency", 0}, 1669 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1670 ACPI_DMT_TERMINATOR 1671 }; 1672 1673 1674 /******************************************************************************* 1675 * 1676 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 1677 * 1678 ******************************************************************************/ 1679 1680 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt[] = 1681 { 1682 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0}, 1683 {ACPI_DMT_UINT24, ACPI_PDTT_OFFSET (Reserved), "Reserved", 0}, 1684 {ACPI_DMT_UINT32, ACPI_PDTT_OFFSET (ArrayOffset), "Array Offset", 0}, 1685 ACPI_DMT_TERMINATOR 1686 }; 1687 1688 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt0[] = 1689 { 1690 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (SubchannelId), "Subchannel Id", 0}, 1691 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1692 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0}, 1693 {ACPI_DMT_FLAG1, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Wait for Completion", 0}, 1694 {ACPI_DMT_FLAG2, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Trigger Order", 0}, 1695 ACPI_DMT_TERMINATOR 1696 }; 1697 1698 1699 /******************************************************************************* 1700 * 1701 * PHAT - Platform Health Assessment Table (ACPI 6.4) 1702 * 1703 ******************************************************************************/ 1704 1705 /* Common subtable header */ 1706 1707 ACPI_DMTABLE_INFO AcpiDmTableInfoPhatHdr[] = 1708 { 1709 {ACPI_DMT_PHAT, ACPI_PHATH_OFFSET (Type), "Subtable Type", 0}, 1710 {ACPI_DMT_UINT16, ACPI_PHATH_OFFSET (Length), "Length", DT_LENGTH}, 1711 {ACPI_DMT_UINT8, ACPI_PHATH_OFFSET (Revision), "Revision", 0}, 1712 ACPI_DMT_TERMINATOR 1713 }; 1714 1715 /* 0: Firmware version table */ 1716 1717 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0[] = 1718 { 1719 {ACPI_DMT_UINT24, ACPI_PHAT0_OFFSET (Reserved), "Reserved", 0}, 1720 {ACPI_DMT_UINT32, ACPI_PHAT0_OFFSET (ElementCount), "Element Count", 0}, 1721 ACPI_DMT_TERMINATOR 1722 }; 1723 1724 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0a[] = 1725 { 1726 {ACPI_DMT_UUID, ACPI_PHAT0A_OFFSET (Guid), "GUID", 0}, 1727 {ACPI_DMT_UINT64, ACPI_PHAT0A_OFFSET (VersionValue), "Version Value", 0}, 1728 {ACPI_DMT_UINT32, ACPI_PHAT0A_OFFSET (ProducerId), "Producer ID", 0}, 1729 ACPI_DMT_TERMINATOR 1730 }; 1731 1732 /* 1: Firmware Health Data Record */ 1733 1734 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1[] = 1735 { 1736 {ACPI_DMT_UINT16, ACPI_PHAT1_OFFSET (Reserved), "Reserved", 0}, 1737 {ACPI_DMT_UINT8, ACPI_PHAT1_OFFSET (Health), "Health", 0}, 1738 {ACPI_DMT_UUID, ACPI_PHAT1_OFFSET (DeviceGuid), "Device GUID", 0}, 1739 {ACPI_DMT_UINT32, ACPI_PHAT1_OFFSET (DeviceSpecificOffset), "Device-Specific Offset", 0}, 1740 ACPI_DMT_TERMINATOR 1741 }; 1742 1743 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1a[] = 1744 { 1745 {ACPI_DMT_UNICODE, 0, "Device Path", 0}, 1746 ACPI_DMT_TERMINATOR 1747 }; 1748 1749 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1b[] = 1750 { 1751 {ACPI_DMT_RAW_BUFFER, 0, "Device-Specific Data", DT_OPTIONAL}, 1752 ACPI_DMT_TERMINATOR 1753 }; 1754 1755 1756 /******************************************************************************* 1757 * 1758 * PMTT - Platform Memory Topology Table 1759 * 1760 ******************************************************************************/ 1761 1762 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[] = 1763 { 1764 {ACPI_DMT_UINT32, ACPI_PMTT_OFFSET (MemoryDeviceCount), "Memory Device Count", 0}, 1765 ACPI_DMT_TERMINATOR 1766 }; 1767 1768 /* Common Subtable header (one per Subtable) */ 1769 1770 #define ACPI_DM_PMTT_HEADER \ 1771 {ACPI_DMT_PMTT, ACPI_PMTTH_OFFSET (Type), "Subtable Type", 0}, \ 1772 {ACPI_DMT_UINT8, ACPI_PMTTH_OFFSET (Reserved1), "Reserved", 0}, \ 1773 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Length), "Length", DT_LENGTH}, \ 1774 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, \ 1775 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0}, \ 1776 {ACPI_DMT_FLAG1, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Physical Element", 0}, \ 1777 {ACPI_DMT_FLAGS2, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Memory Type", 0}, \ 1778 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Reserved2), "Reserved", 0}, \ 1779 {ACPI_DMT_UINT32, ACPI_PMTTH_OFFSET (MemoryDeviceCount), "Memory Device Count", 0} 1780 1781 /* PMTT Subtables */ 1782 1783 /* 0: Socket */ 1784 1785 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[] = 1786 { 1787 ACPI_DM_PMTT_HEADER, 1788 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (SocketId), "Socket ID", 0}, 1789 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (Reserved), "Reserved", 0}, 1790 ACPI_DMT_TERMINATOR 1791 }; 1792 1793 /* 1: Memory Controller */ 1794 1795 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[] = 1796 { 1797 ACPI_DM_PMTT_HEADER, 1798 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (ControllerId), "Controller ID", 0}, 1799 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Reserved), "Reserved", 0}, 1800 ACPI_DMT_TERMINATOR 1801 }; 1802 1803 /* 2: Physical Component */ 1804 1805 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt2[] = 1806 { 1807 ACPI_DM_PMTT_HEADER, 1808 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (BiosHandle), "Bios Handle", 0}, 1809 ACPI_DMT_TERMINATOR 1810 }; 1811 1812 /* 0xFF: Vendor Specific */ 1813 1814 ACPI_DMTABLE_INFO AcpiDmTableInfoPmttVendor[] = 1815 { 1816 ACPI_DM_PMTT_HEADER, 1817 {ACPI_DMT_UUID, ACPI_PMTT_VENDOR_OFFSET (TypeUuid), "Type Uuid", 0}, 1818 {ACPI_DMT_PMTT_VENDOR, ACPI_PMTT_VENDOR_OFFSET (Specific), "Vendor Data", 0}, 1819 ACPI_DMT_TERMINATOR 1820 }; 1821 1822 1823 /******************************************************************************* 1824 * 1825 * PPTT - Processor Properties Topology Table (ACPI 6.2) 1826 * 1827 ******************************************************************************/ 1828 1829 /* Main table consists of only the standard ACPI header - subtables follow */ 1830 1831 /* Common Subtable header (one per Subtable) */ 1832 1833 ACPI_DMTABLE_INFO AcpiDmTableInfoPpttHdr[] = 1834 { 1835 {ACPI_DMT_PPTT, ACPI_PPTTH_OFFSET (Type), "Subtable Type", 0}, 1836 {ACPI_DMT_UINT8, ACPI_PPTTH_OFFSET (Length), "Length", 0}, 1837 ACPI_DMT_TERMINATOR 1838 }; 1839 1840 /* 0: Processor hierarchy node */ 1841 1842 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0[] = 1843 { 1844 {ACPI_DMT_UINT16, ACPI_PPTT0_OFFSET (Reserved), "Reserved", 0}, 1845 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1846 {ACPI_DMT_FLAG0, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Physical package", 0}, 1847 {ACPI_DMT_FLAG1, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "ACPI Processor ID valid", 0}, 1848 {ACPI_DMT_FLAG2, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Processor is a thread", 0}, 1849 {ACPI_DMT_FLAG3, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Node is a leaf", 0}, 1850 {ACPI_DMT_FLAG4, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Identical Implementation", 0}, 1851 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Parent), "Parent", 0}, 1852 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (AcpiProcessorId), "ACPI Processor ID", 0}, 1853 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (NumberOfPrivResources), "Private Resource Number", 0}, 1854 ACPI_DMT_TERMINATOR 1855 }; 1856 1857 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0a[] = 1858 { 1859 {ACPI_DMT_UINT32, 0, "Private Resource", DT_OPTIONAL}, 1860 ACPI_DMT_TERMINATOR 1861 }; 1862 1863 /* 1: Cache type */ 1864 1865 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1[] = 1866 { 1867 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (Reserved), "Reserved", 0}, 1868 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1869 {ACPI_DMT_FLAG0, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Size valid", 0}, 1870 {ACPI_DMT_FLAG1, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 1871 {ACPI_DMT_FLAG2, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 1872 {ACPI_DMT_FLAG3, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 1873 {ACPI_DMT_FLAG4, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 1874 {ACPI_DMT_FLAG5, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 1875 {ACPI_DMT_FLAG6, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 1876 {ACPI_DMT_FLAG7, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache ID valid", 0}, 1877 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 1878 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Size), "Size", 0}, 1879 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NumberOfSets), "Number of Sets", 0}, 1880 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Associativity), "Associativity", 0}, 1881 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Attributes), "Attributes", 0}, 1882 {ACPI_DMT_FLAGS0, ACPI_PPTT1_OFFSET (Attributes), "Allocation Type", 0}, 1883 {ACPI_DMT_FLAGS2, ACPI_PPTT1_OFFSET (Attributes), "Cache Type", 0}, 1884 {ACPI_DMT_FLAG4, ACPI_PPTT1_OFFSET (Attributes), "Write Policy", 0}, 1885 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (LineSize), "Line Size", 0}, 1886 ACPI_DMT_TERMINATOR 1887 }; 1888 1889 /* 1: cache type v1 */ 1890 1891 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1a[] = 1892 { 1893 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (CacheId), "Cache ID", 0}, 1894 ACPI_DMT_TERMINATOR 1895 }; 1896 1897 /* 2: ID */ 1898 1899 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt2[] = 1900 { 1901 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (Reserved), "Reserved", 0}, 1902 {ACPI_DMT_UINT32, ACPI_PPTT2_OFFSET (VendorId), "Vendor ID", 0}, 1903 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level1Id), "Level1 ID", 0}, 1904 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level2Id), "Level2 ID", 0}, 1905 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MajorRev), "Major revision", 0}, 1906 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MinorRev), "Minor revision", 0}, 1907 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (SpinRev), "Spin revision", 0}, 1908 ACPI_DMT_TERMINATOR 1909 }; 1910 1911 1912 /******************************************************************************* 1913 * 1914 * PRMT - Platform Runtime Mechanism Table 1915 * Version 1 1916 * 1917 ******************************************************************************/ 1918 1919 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHdr[] = 1920 { 1921 {ACPI_DMT_UUID, ACPI_PRMTH_OFFSET (PlatformGuid[0]), "Platform GUID", 0}, 1922 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoOffset), "Module info offset", 0}, 1923 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoCount), "Module info count", 0}, 1924 ACPI_DMT_NEW_LINE, 1925 ACPI_DMT_TERMINATOR 1926 1927 }; 1928 1929 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtModule[] = 1930 { 1931 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Revision), "Revision", 0}, 1932 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Length), "Length", 0}, 1933 {ACPI_DMT_UUID, ACPI_PRMT0_OFFSET (ModuleGuid[0]), "Module GUID", 0}, 1934 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MajorRev), "Major Revision", 0}, 1935 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MinorRev), "Minor Revision", 0}, 1936 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (HandlerInfoCount), "Handler Info Count", 0}, 1937 {ACPI_DMT_UINT32, ACPI_PRMT0_OFFSET (HandlerInfoOffset), "Handler Info Offset", 0}, 1938 {ACPI_DMT_UINT64, ACPI_PRMT0_OFFSET (MmioListPointer), "Mmio List pointer", 0}, 1939 ACPI_DMT_NEW_LINE, 1940 ACPI_DMT_TERMINATOR 1941 1942 }; 1943 1944 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHandler[] = 1945 { 1946 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Revision), "Revision", 0}, 1947 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Length), "Length", 0}, 1948 {ACPI_DMT_UUID, ACPI_PRMT1_OFFSET (HandlerGuid[0]), "Handler GUID", 0}, 1949 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (HandlerAddress), "Handler address", 0}, 1950 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (StaticDataBufferAddress),"Static Data Address", 0}, 1951 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (AcpiParamBufferAddress), "ACPI Parameter Address", 0}, 1952 ACPI_DMT_NEW_LINE, 1953 ACPI_DMT_TERMINATOR 1954 1955 }; 1956 1957 1958 /******************************************************************************* 1959 * 1960 * RASF - RAS Feature table 1961 * 1962 ******************************************************************************/ 1963 1964 ACPI_DMTABLE_INFO AcpiDmTableInfoRasf[] = 1965 { 1966 {ACPI_DMT_BUF12, ACPI_RASF_OFFSET (ChannelId[0]), "Channel ID", 0}, 1967 ACPI_DMT_TERMINATOR 1968 }; 1969 1970 1971 /******************************************************************************* 1972 * 1973 * RAS2 - RAS2 Feature table (ACPI 6.5) 1974 * 1975 ******************************************************************************/ 1976 1977 ACPI_DMTABLE_INFO AcpiDmTableInfoRas2[] = 1978 { 1979 {ACPI_DMT_UINT16, ACPI_RAS2_OFFSET (Reserved), "Reserved", 0}, 1980 {ACPI_DMT_UINT16, ACPI_RAS2_OFFSET (NumPccDescs), "Number of PCC Descriptors", 0}, 1981 ACPI_DMT_TERMINATOR 1982 }; 1983 1984 /* RAS2 PCC Descriptor */ 1985 1986 ACPI_DMTABLE_INFO AcpiDmTableInfoRas2PccDesc[] = 1987 { 1988 {ACPI_DMT_UINT8, ACPI_RAS2_PCC_DESC_OFFSET (ChannelId), "Channel ID", 0}, 1989 {ACPI_DMT_UINT16, ACPI_RAS2_PCC_DESC_OFFSET (Reserved), "Reserved", 0}, 1990 {ACPI_DMT_UINT8, ACPI_RAS2_PCC_DESC_OFFSET (FeatureType), "Feature Type", 0}, 1991 {ACPI_DMT_UINT32, ACPI_RAS2_PCC_DESC_OFFSET (Instance), "Instance", 0}, 1992 ACPI_DMT_TERMINATOR 1993 }; 1994 1995 1996 /******************************************************************************* 1997 * 1998 * RGRT - Regulatory Graphics Resource Table 1999 * 2000 ******************************************************************************/ 2001 2002 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt[] = 2003 { 2004 {ACPI_DMT_UINT16, ACPI_RGRT_OFFSET (Version), "Version", 0}, 2005 {ACPI_DMT_RGRT, ACPI_RGRT_OFFSET (ImageType), "Image Type", 0}, 2006 {ACPI_DMT_UINT8, ACPI_RGRT_OFFSET (Reserved), "Reserved", 0}, 2007 ACPI_DMT_TERMINATOR 2008 }; 2009 2010 /* 2011 * We treat the binary image field as its own subtable (to make 2012 * ACPI_DMT_RAW_BUFFER work properly). 2013 */ 2014 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt0[] = 2015 { 2016 {ACPI_DMT_RAW_BUFFER, 0, "Image", 0}, 2017 ACPI_DMT_TERMINATOR 2018 }; 2019 2020 2021 /******************************************************************************* 2022 * 2023 * RHCT - RISC-V Hart Capabilities Table 2024 * 2025 ******************************************************************************/ 2026 2027 ACPI_DMTABLE_INFO AcpiDmTableInfoRhct[] = 2028 { 2029 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (Flags), "Flags", 0}, 2030 {ACPI_DMT_UINT64, ACPI_RHCT_OFFSET (TimeBaseFreq), "Timer Base Frequency", 0}, 2031 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeCount), "Number of nodes", 0}, 2032 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeOffset), "Offset to the node array", 0}, 2033 ACPI_DMT_TERMINATOR 2034 }; 2035 2036 2037 /* Common Subtable header (one per Subtable) */ 2038 2039 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctNodeHdr[] = 2040 { 2041 {ACPI_DMT_RHCT, ACPI_RHCTH_OFFSET (Type), "Subtable Type", 0}, 2042 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Length), "Length", 0}, 2043 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Revision), "Revision", 0}, 2044 ACPI_DMT_TERMINATOR 2045 }; 2046 2047 /* 0: ISA string type */ 2048 2049 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsa1[] = 2050 { 2051 {ACPI_DMT_UINT16, ACPI_RHCT0_OFFSET (IsaLength), "ISA string length", 0}, 2052 {ACPI_DMT_STRING, ACPI_RHCT0_OFFSET (Isa[0]), "ISA string", 0}, 2053 ACPI_DMT_TERMINATOR 2054 }; 2055 2056 2057 /* Optional padding field */ 2058 2059 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsaPad[] = 2060 { 2061 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 2062 ACPI_DMT_TERMINATOR 2063 }; 2064 2065 /* 1: CMO node type */ 2066 2067 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctCmo1[] = 2068 { 2069 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (Reserved), "Reserved", 0}, 2070 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbomSize), "CBOM Block Size", 0}, 2071 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbopSize), "CBOP Block Size", 0}, 2072 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbozSize), "CBOZ Block Size", 0}, 2073 ACPI_DMT_TERMINATOR 2074 }; 2075 2076 /* 2: MMU node type */ 2077 2078 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctMmu1[] = 2079 { 2080 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (Reserved), "Reserved", 0}, 2081 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (MmuType), "MMU Type", 0}, 2082 ACPI_DMT_TERMINATOR 2083 }; 2084 2085 /* 0xFFFF: Hart Info type */ 2086 2087 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo1[] = 2088 { 2089 {ACPI_DMT_UINT16, ACPI_RHCTFFFF_OFFSET (NumOffsets), "Number of offsets", 0}, 2090 {ACPI_DMT_UINT32, ACPI_RHCTFFFF_OFFSET (Uid), "Processor UID", 0}, 2091 ACPI_DMT_TERMINATOR 2092 }; 2093 2094 2095 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo2[] = 2096 { 2097 {ACPI_DMT_UINT32, 0, "Nodes", DT_OPTIONAL}, 2098 ACPI_DMT_TERMINATOR 2099 }; 2100 2101 2102 /******************************************************************************* 2103 * 2104 * S3PT - S3 Performance Table 2105 * 2106 ******************************************************************************/ 2107 2108 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt[] = 2109 { 2110 {ACPI_DMT_SIG, ACPI_S3PT_OFFSET (Signature[0]), "Signature", 0}, 2111 {ACPI_DMT_UINT32, ACPI_S3PT_OFFSET (Length), "Length", DT_LENGTH}, 2112 ACPI_DMT_TERMINATOR 2113 }; 2114 2115 /* S3PT subtable header */ 2116 2117 ACPI_DMTABLE_INFO AcpiDmTableInfoS3ptHdr[] = 2118 { 2119 {ACPI_DMT_UINT16, ACPI_S3PTH_OFFSET (Type), "Type", 0}, 2120 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Length), "Length", DT_LENGTH}, 2121 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Revision), "Revision", 0}, 2122 ACPI_DMT_TERMINATOR 2123 }; 2124 2125 /* 0: Basic S3 Resume Performance Record */ 2126 2127 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt0[] = 2128 { 2129 {ACPI_DMT_UINT32, ACPI_S3PT0_OFFSET (ResumeCount), "Resume Count", 0}, 2130 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (FullResume), "Full Resume", 0}, 2131 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (AverageResume), "Average Resume", 0}, 2132 ACPI_DMT_TERMINATOR 2133 }; 2134 2135 /* 1: Basic S3 Suspend Performance Record */ 2136 2137 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt1[] = 2138 { 2139 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendStart), "Suspend Start", 0}, 2140 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendEnd), "Suspend End", 0}, 2141 ACPI_DMT_TERMINATOR 2142 }; 2143 2144 2145 /******************************************************************************* 2146 * 2147 * SBST - Smart Battery Specification Table 2148 * 2149 ******************************************************************************/ 2150 2151 ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] = 2152 { 2153 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level", 0}, 2154 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level", 0}, 2155 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level", 0}, 2156 ACPI_DMT_TERMINATOR 2157 }; 2158 2159 2160 /******************************************************************************* 2161 * 2162 * SDEI - Software Delegated Exception Interface Descriptor Table 2163 * 2164 ******************************************************************************/ 2165 2166 ACPI_DMTABLE_INFO AcpiDmTableInfoSdei[] = 2167 { 2168 ACPI_DMT_TERMINATOR 2169 }; 2170 2171 2172 /******************************************************************************* 2173 * 2174 * SDEV - Secure Devices Table (ACPI 6.2) 2175 * 2176 ******************************************************************************/ 2177 2178 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev[] = 2179 { 2180 ACPI_DMT_TERMINATOR 2181 }; 2182 2183 /* Common Subtable header (one per Subtable) */ 2184 2185 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevHdr[] = 2186 { 2187 {ACPI_DMT_SDEV, ACPI_SDEVH_OFFSET (Type), "Subtable Type", 0}, 2188 {ACPI_DMT_UINT8, ACPI_SDEVH_OFFSET (Flags), "Flags (decoded below)", 0}, 2189 {ACPI_DMT_FLAG0, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Allow handoff to unsecure OS", 0}, 2190 {ACPI_DMT_FLAG1, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Secure access components present", 0}, 2191 {ACPI_DMT_UINT16, ACPI_SDEVH_OFFSET (Length), "Length", DT_LENGTH}, 2192 ACPI_DMT_TERMINATOR 2193 }; 2194 2195 /* SDEV Subtables */ 2196 2197 /* 0: Namespace Device Based Secure Device Structure */ 2198 2199 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0[] = 2200 { 2201 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdOffset), "Device ID Offset", 0}, 2202 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdLength), "Device ID Length", 0}, 2203 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2204 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2205 ACPI_DMT_TERMINATOR 2206 }; 2207 2208 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0a[] = 2209 { 2210 {ACPI_DMT_STRING, 0, "Namepath", 0}, 2211 ACPI_DMT_TERMINATOR 2212 }; 2213 2214 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0b[] = 2215 { 2216 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentOffset), "Secure Access Components Offset", 0}, 2217 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentLength), "Secure Access Components Length", 0}, 2218 ACPI_DMT_TERMINATOR 2219 }; 2220 2221 /* Secure access components */ 2222 2223 /* Common secure access components header secure access component */ 2224 2225 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompHdr[] = 2226 { 2227 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Type), "Secure Component Type", 0}, 2228 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Flags), "Flags (decoded below)", 0}, 2229 {ACPI_DMT_UINT16, ACPI_SDEVCH_OFFSET (Length), "Length", 0}, 2230 ACPI_DMT_TERMINATOR 2231 }; 2232 2233 /* 0: Identification Based Secure Access Component */ 2234 2235 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompId[] = 2236 { 2237 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdOffset), "Hardware ID Offset", 0}, 2238 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdLength), "Hardware ID Length", 0}, 2239 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdOffset), "Subsystem ID Offset", 0}, 2240 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdLength), "Subsystem ID Length", 0}, 2241 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareRevision), "Hardware Revision", 0}, 2242 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (HardwareRevPresent), "Hardware Rev Present", 0}, 2243 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (ClassCodePresent), "Class Code Present", 0}, 2244 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciBaseClass), "PCI Base Class", 0}, 2245 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciSubClass), "PCI SubClass", 0}, 2246 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciProgrammingXface), "PCI Programming Xface", 0}, 2247 ACPI_DMT_TERMINATOR 2248 }; 2249 2250 /* 1: Memory Based Secure Access Component */ 2251 2252 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompMem[] = 2253 { 2254 {ACPI_DMT_UINT32, ACPI_SDEVC1_OFFSET (Reserved), "Reserved", 0}, 2255 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryBaseAddress), "Memory Base Address", 0}, 2256 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryLength), "Memory Length", 0}, 2257 ACPI_DMT_TERMINATOR 2258 }; 2259 2260 2261 /* 1: PCIe Endpoint Device Based Device Structure */ 2262 2263 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1[] = 2264 { 2265 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (Segment), "Segment", 0}, 2266 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (StartBus), "Start Bus", 0}, 2267 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathOffset), "Path Offset", 0}, 2268 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathLength), "Path Length", 0}, 2269 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2270 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2271 ACPI_DMT_TERMINATOR 2272 }; 2273 2274 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1a[] = 2275 { 2276 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Device), "Device", 0}, 2277 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Function), "Function", 0}, 2278 ACPI_DMT_TERMINATOR 2279 }; 2280 2281 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1b[] = 2282 { 2283 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, /*, DT_OPTIONAL}, */ 2284 ACPI_DMT_TERMINATOR 2285 }; 2286 2287 /*! [End] no source code translation !*/ 2288