1 /* $NetBSD: octeon_asxreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * ASX Registers 31 */ 32 33 #ifndef _OCTEON_ASXREG_H_ 34 #define _OCTEON_ASXREG_H_ 35 36 #define ASX0_RX_PRT_EN 0x00011800b0000000ULL 37 #define ASX0_TX_PRT_EN 0x00011800b0000008ULL 38 #define ASX0_INT_REG 0x00011800b0000010ULL 39 #define ASX0_INT_EN 0x00011800b0000018ULL 40 #define ASX0_RX_CLK_SET0 0x00011800b0000020ULL 41 #define ASX0_RX_CLK_SET1 0x00011800b0000028ULL 42 #define ASX0_RX_CLK_SET2 0x00011800b0000030ULL 43 #define ASX0_PRT_LOOP 0x00011800b0000040ULL 44 #define ASX0_TX_CLK_SET0 0x00011800b0000048ULL 45 #define ASX0_TX_CLK_SET1 0x00011800b0000050ULL 46 #define ASX0_TX_CLK_SET2 0x00011800b0000058ULL 47 #define ASX0_COMP_BYP 0x00011800b0000068ULL 48 #define ASX0_TX_HI_WATER000 0x00011800b0000080ULL 49 #define ASX0_TX_HI_WATER001 0x00011800b0000088ULL 50 #define ASX0_TX_HI_WATER002 0x00011800b0000090ULL 51 #define ASX0_GMII_RX_CLK_SET 0x00011800b0000180ULL 52 #define ASX0_GMII_RX_DAT_SET 0x00011800b0000188ULL 53 #define ASX0_MII_RX_DAT_SET 0x00011800b0000190ULL 54 55 #define ASX0_BASE 0x00011800b0000000ULL 56 #define ASX0_SIZE 0x0198ULL 57 58 #define ASX0_RX_PRT_EN_OFFSET 0x0000 59 #define ASX0_TX_PRT_EN_OFFSET 0x0008 60 #define ASX0_INT_REG_OFFSET 0x0010 61 #define ASX0_INT_EN_OFFSET 0x0018 62 #define ASX0_RX_CLK_SET0_OFFSET 0x0020 63 #define ASX0_RX_CLK_SET1_OFFSET 0x0028 64 #define ASX0_RX_CLK_SET2_OFFSET 0x0030 65 #define ASX0_PRT_LOOP_OFFSET 0x0040 66 #define ASX0_TX_CLK_SET0_OFFSET 0x0048 67 #define ASX0_TX_CLK_SET1_OFFSET 0x0050 68 #define ASX0_TX_CLK_SET2_OFFSET 0x0058 69 #define ASX0_COMP_BYP_OFFSET 0x0068 70 #define ASX0_TX_HI_WATER000_OFFSET 0x0080 71 #define ASX0_TX_HI_WATER001_OFFSET 0x0088 72 #define ASX0_TX_HI_WATER002_OFFSET 0x0090 73 #define ASX0_GMII_RX_CLK_SET_OFFSET 0x0180 74 #define ASX0_GMII_RX_DAT_SET_OFFSET 0x0188 75 #define ASX0_MII_RX_DAT_SET_OFFSET 0x0190 76 77 /* XXX */ 78 79 80 /* 81 * ASX_RX_PRT_EN 82 */ 83 #define ASX0_RX_PRT_EN_63_3 0xfffffff8 84 #define ASX0_RX_PRT_EN_PRT_EN 0x00000007 85 86 /* 87 * ASX0_TX_PRT_EN 88 */ 89 #define ASX0_TX_PRT_EN_63_3 0xfffffff8 90 #define ASX0_TX_PRT_EN_PRT_EN 0x00000007 91 92 /* 93 * ASX0_INT_REG 94 */ 95 #define ASX0_INT_REG_63_11 0xfffff800 96 #define ASX0_INT_REG_TXPSH 0x00000700 97 #define ASX0_INT_REG_7 UINT32_C(0x00000080) 98 #define ASX0_INT_REG_TXPOP 0x00000070 99 #define ASX0_INT_REG_3 UINT32_C(0x00000008) 100 #define ASX0_INT_REG_OVRFLW 0x00000007 101 102 /* 103 * ASX0_INT_EN 104 */ 105 #define ASX0_INT_EN_63_11 0xfffff800 106 #define ASX0_INT_EN_TXPSH 0x00000700 107 #define ASX0_INT_EN_7 UINT32_C(0x00000080) 108 #define ASX0_INT_EN_TXPOP 0x00000070 109 #define ASX0_INT_EN_3 UINT32_C(0x00000008) 110 #define ASX0_INT_EN_OVRFLW 0x00000007 111 112 /* 113 * ASX0_RX_CLK_SET 114 */ 115 #define ASX0_RX_CLK_SET_63_5 0xffffffe0 116 #define ASX0_RX_CLK_SET_SETTING 0x0000001f 117 118 /* 119 * ASX0_RRT_LOOP 120 */ 121 #define ASX0_PRT_LOOP_63_7 0xffffff80 122 #define ASX0_PRT_LOOP_EXT_LOOP 0x00000070 123 #define ASX0_PRT_LOOP_3 UINT32_C(0x00000008) 124 #define ASX0_PRT_LOOP_PRT_LOOP 0x00000007 125 126 /* 127 * ASX0_TX_CLK_SET 128 */ 129 #define ASX0_TX_CLK_SET_63_5 0xffffffe0 130 #define ASX0_TX_CLK_SET_SETTING 0x0000001f 131 132 /* 133 * ASX0_TX_COMP_BYP 134 */ 135 #define ASX0_TX_COMP_BYP_63_9 0xfffffe00 136 #define ASX0_TX_COMP_BYP_BYPASS UINT32_C(0x00000100) 137 #define ASX0_TX_COMP_BYP_PCTL 0x000000f0 138 #define ASX0_TX_COMP_BYP_NCTL 0x0000000f 139 140 /* 141 * ASX0_TX_HI_WATER 142 */ 143 #define ASX0_TX_HI_WATER_63_3 0xfffffff8 144 #define ASX0_TX_HI_WATER_MARK 0x00000007 145 146 /* 147 * ASX0_GMXII_RX_CLK_SET 148 */ 149 #define ASX0_GMII_RX_CLK_SET_63_5 0xffffffe0 150 #define ASX0_GMII_RX_CLK_SET_SETTING 0x0000001f 151 152 /* 153 * ASX0_GMXII_RX_DAT_SET 154 */ 155 #define ASX0_GMII_RX_DAT_SET_63_5 0xffffffe0 156 #define ASX0_GMII_RX_DAT_SET_SETTING 0x0000001f 157 158 #endif /* _OCTEON_ASXREG_H_ */ 159