Changes in interleavevectorization.ll

1157187496afbbb203b8ec7aa320769ec6eed8c4 - [VPlan] Propagate all GEP flags (#119899)

Tue, 17 Dec 2024 12:48:50 +0000

[VPlan] Propagate all GEP flags (#119899)Store GEPNoWrapFlags instead of only InBounds and propagate them. List of files: /llvm-project/llvm/test/Transforms/PhaseOrdering/AArch64/interleavevectorization.ll

7f74651837b8f95996ea4c774b2e604020446951 - [VPlan] Use pointer to member 0 as VPInterleaveRecipe's pointer arg. (#106431)

Sun, 06 Oct 2024 21:53:13 +0000

[VPlan] Use pointer to member 0 as VPInterleaveRecipe's pointer arg. (#106431)Update VPInterleaveRecipe to always use the pointer to member 0 as pointer argument. This in many cases helps to remove unneeded index adjustments and simplifies VPInterleaveRecipe::execute. In some rare cases, the address of member 0 does not dominate the insert position of the interleave group. In those cases a PtrAdd VPInstruction is emitted to compute the address of member 0 based on the address of the insert position. Alternatively we could hoist the recipe computing the address of member 0. List of files: /llvm-project/llvm/test/Transforms/PhaseOrdering/AArch64/interleavevectorization.ll

efa8463ab90147aacd4647eb7715763978235890 - [VectorCombine] Add free concats to shuffleToIdentity. (#94954)

Tue, 25 Jun 2024 06:55:08 +0000

[VectorCombine] Add free concats to shuffleToIdentity. (#94954)This is another relatively small adjustment to shuffleToIdentity, which has had a few knock-one effects to need a few more changes. It attempts to detect free concats, that will be legalized to multiple vector operations. For example if the lanes are '[a[0], a[1], b[0], b[1]]' and a and b are v2f64 under aarch64. In order to do this: - isFreeConcat detects whether the input has piece-wise identities from multiple inputs that can become a concat. - A tree of concat shuffles is created to concatenate the input values into a single vector. This is a little different to most other inputs as there are created from multiple values that are being combined together, and we cannot rely on the Lane0 insert location always being valid. - The insert location is changed to the original location instead of updating per item, which ensure it is valid due to the order that we visit and create items. List of files: /llvm-project/llvm/test/Transforms/PhaseOrdering/AArch64/interleavevectorization.ll

a4d10266d20bfe5930dfed77e17832af341ed66e - [VectorCombine] Add foldShuffleToIdentity (#88693)

Fri, 03 May 2024 18:14:38 +0000

[VectorCombine] Add foldShuffleToIdentity (#88693)This patch adds a basic version of a combine that attempts to remove shuffles that when combined simplify away to an identity shuffle. For example: %ab = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> %at = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> %abt = fneg <4 x half> %at %abb = fneg <4 x half> %ab %r = shufflevector <4 x half> %abt, <4 x half> %abb, <8 x i32> By looking through the shuffles and fneg, it can be simplified to: %r = fneg <8 x half> %a The code tracks each lane starting from the original shuffle, keeping a track of a vector of {src, idx}. As we propagate up through the instructions we will either look through intermediate instructions (binops and unops) or see a collections of lanes that all have the same src and incrementing idx (an identity). We can also see a single value with identical lanes, which we can treat like a splat. Only the basic version is added here, handling identities, splats, binops and unops. In follow-up patches other instructions can be added such as constants, intrinsics, cmp/sel and zext/sext/trunc. List of files: /llvm-project/llvm/test/Transforms/PhaseOrdering/AArch64/interleavevectorization.ll

bddfbe748ba5fa4363bb343687841f5f389e38f8 - [VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (#88743)

Mon, 22 Apr 2024 14:57:59 +0000

[VectorCombine] foldShuffleOfShuffles - fold "shuffle (shuffle x, undef), (shuffle y, undef)" -> "shuffle x, y" (#88743)Another step towards cleaning up shuffles that have been split, often across bitcasts between SSE intrinsic. Strip shuffles entirely if we fold to an identity shuffle. List of files: /llvm-project/llvm/test/Transforms/PhaseOrdering/AArch64/interleavevectorization.ll

87d36c5d8285b61f3e39b3f63d5eced733bd9d3e - [AArch64] Add phase ordering tests for some basic interleaving vectorization patterns. NFC

Sat, 20 Apr 2024 14:52:09 +0000

[AArch64] Add phase ordering tests for some basic interleaving vectorization patterns. NFC List of files: /llvm-project/llvm/test/Transforms/PhaseOrdering/AArch64/interleavevectorization.ll