Changes in split-vecpred.ll

2208c97c1bec2512d4e47b6223db6d95a7037956 - [Hexagon,test] Change llc -march= to -mtriple=

Sun, 15 Dec 2024 18:20:22 +0000

[Hexagon,test] Change llc -march= to -mtriple=Similar to 806761a7629df268c8aed49657aeccffa6bca449-mtriple= specifies the full target triple while -march= merely sets thearchitecture part of the default target triple, leaving a target triple whichmay not make sense.Therefore, -march= is error-prone and not recommended for tests without a targettriple. The issue has been benign as we recognize $unknown-apple-darwin as ELF insteadof rejecting it outrightly. List of files: /llvm-project/llvm/test/CodeGen/Hexagon/split-vecpred.ll

a96f691985c8546e826012fdc3481c88f034a194 - [Hexagon] Convert some tests to opaque pointers (NFC)

Mon, 19 Dec 2022 11:52:45 +0000

[Hexagon] Convert some tests to opaque pointers (NFC) List of files: /llvm-project/llvm/test/CodeGen/Hexagon/split-vecpred.ll

b1d47467e26142e6029e9ec7ca5c42645ffaa7bb - [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1

Fri, 07 Feb 2020 15:33:18 +0000

[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1This commit removes the artificial types <512 x i1> and <1024 x i1>from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal onHexagon.It may cause existing bitcode files to become invalid.* Converting between vector predicates and vector registers must be done explicitly via vandvrt/vandqrt instructions (their intrinsics), i.e. (for 64-byte mode): %Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1) %V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1) The conversion intrinsics are: declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32) declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32) They are all pure.* Vector predicate values cannot be loaded/stored directly. This directly reflects the architecture restriction. Loading and storing or vector predicates must be done indirectly via vector registers and explicit conversions via vandvrt/vandqrt instructions. List of files: /llvm-project/llvm/test/CodeGen/Hexagon/split-vecpred.ll

046090db5330dd87e54a7b46ec34384dd3b43c31 - [Hexagon] Add more lit tests

Mon, 12 Mar 2018 14:01:28 +0000

[Hexagon] Add more lit testsllvm-svn: 327271 List of files: /llvm-project/llvm/test/CodeGen/Hexagon/split-vecpred.ll