en Copyright 2015 Java http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll#2208c97c1bec2512d4e47b6223db6d95a7037956 [Hexagon,test] Change llc -march= to -mtriple=Similar to 806761a7629df268c8aed49657aeccffa6bca449-mtriple= specifies the full target triple while -march= merely sets thearchitecture part of the default target triple, leaving a target triple whichmay not make sense.Therefore, -march= is error-prone and not recommended for tests without a targettriple. The issue has been benign as we recognize $unknown-apple-darwin as ELF insteadof rejecting it outrightly. List of files: /llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll Sun, 15 Dec 2024 18:20:22 +0000 Fangrui Song <i@maskray.me> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll#a96f691985c8546e826012fdc3481c88f034a194 [Hexagon] Convert some tests to opaque pointers (NFC) List of files: /llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll Mon, 19 Dec 2022 11:52:45 +0000 Nikita Popov <npopov@redhat.com> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll#884b919f2e104b8316a3cda21ecef8d22ba3a3d3 Reapply [Hexagon] Use default attributes for intrinsicsThe issue that caused the revert has been fixed in:44bd80751274a81c870882968ecd478b03af292a-----This switches Hexagon intrinsics to use the default attributes(nosync, nofree, nocallback and willreturn). Especially willreturnis needed to prevent optimization regressions in the future.The only intrinsics I've excluded here are the load/store lockedintrinsics, which presumably aren't nosync.Differential Revision: https://reviews.llvm.org/D137623 List of files: /llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll Tue, 08 Nov 2022 10:48:03 +0000 Nikita Popov <npopov@redhat.com> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll#57dbca20eae8db0fd17cc59fe98c7804f02d6644 Revert "[Hexagon] Use default attributes for intrinsics"This reverts commit 8a8983b279dd5e4dceabe1fadbb8980b6adb88f9.Uncovers existing regalloc issue in Hexagon backend - blocking for HalideHexagon users. Reverting to unblock, to be recommitted when underlying issue is resolved.Reproducer available shortly. List of files: /llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll Fri, 11 Nov 2022 22:57:10 +0000 Alina Sbirlea <asbirlea@google.com> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll#8a8983b279dd5e4dceabe1fadbb8980b6adb88f9 [Hexagon] Use default attributes for intrinsicsThis switches Hexagon intrinsics to use the default attributes(nosync, nofree, nocallback and willreturn). Especially willreturnis needed to prevent optimization regressions in the future.The only intrinsics I've excluded here are the load/store lockedintrinsics, which presumably aren't nosync.Differential Revision: https://reviews.llvm.org/D137623 List of files: /llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll Tue, 08 Nov 2022 10:48:03 +0000 Nikita Popov <npopov@redhat.com> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll#2819e5de42e03f100c9a90c1328465e99d28ee5d [Hexagon] Handle instruction selection for select(I1,Q,Q)Lower select(I1,Q,Q) by converting vector predicate Q to vector register V,doing select(I1,V,V), and then converting the resulting V back to Q. Also,try to avoid creating such situations in the first place. List of files: /llvm-project/llvm/test/CodeGen/Hexagon/select-vector-pred.ll Thu, 16 Apr 2020 20:56:56 +0000 Ikhlas Ajbar <iajbar@quicinc.com>