en Copyright 2015 Java http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll#2208c97c1bec2512d4e47b6223db6d95a7037956 [Hexagon,test] Change llc -march= to -mtriple=Similar to 806761a7629df268c8aed49657aeccffa6bca449-mtriple= specifies the full target triple while -march= merely sets thearchitecture part of the default target triple, leaving a target triple whichmay not make sense.Therefore, -march= is error-prone and not recommended for tests without a targettriple. The issue has been benign as we recognize $unknown-apple-darwin as ELF insteadof rejecting it outrightly. List of files: /llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll Sun, 15 Dec 2024 18:20:22 +0000 Fangrui Song <i@maskray.me> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll#a96f691985c8546e826012fdc3481c88f034a194 [Hexagon] Convert some tests to opaque pointers (NFC) List of files: /llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll Mon, 19 Dec 2022 11:52:45 +0000 Nikita Popov <npopov@redhat.com> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll#a72fad980cb18a09dbd6ea95d3b5684d3280894a [Hexagon] Replace instruction definitions with auto-generated onesllvm-svn: 294753 List of files: /llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll Fri, 10 Feb 2017 15:33:13 +0000 Krzysztof Parzyszek <kparzysz@codeaurora.org> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll#254f889dc54672f6765791078a5c22a71e2b7cb3 MachinePipeliner pass that implements Swing Modulo SchedulingSoftware pipelining is an optimization for improving ILP byoverlapping loop iterations. Swing Modulo Scheduling (SMS) isan implementation of software pipelining that attempts toreduce register pressure and generate efficient pipelines witha low compile-time cost.This implementaion of SMS is a target-independent back-end pass.When enabled, the pass should run just prior to the registerallocation pass, while the machine IR is in SSA form. If the passis successful, then the original loop is replaced by the optimizedloop. The optimized loop contains one or more prolog blocks, thepipelined kernel, and one or more epilog blocks.This pass is enabled for Hexagon only. To enable for other targets,a couple of target specific hooks must be implemented, and thepass needs to be called from the target's TargetMachineimplementation.Differential Review: http://reviews.llvm.org/D16829llvm-svn: 277169 List of files: /llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll Fri, 29 Jul 2016 16:44:44 +0000 Brendon Cahoon <bcahoon@codeaurora.org> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll#bece8edcdde53f9854a7edfc27890333281541cc [Hexagon] Generate more hardware loopsRefactored parts of the hardware loop pass to generatemore. Also, added more tests.Differential Revision: http://reviews.llvm.org/D9568llvm-svn: 236896 List of files: /llvm-project/llvm/test/CodeGen/Hexagon/hwloop1.ll Fri, 08 May 2015 20:18:21 +0000 Brendon Cahoon <bcahoon@codeaurora.org>