en Copyright 2015 Java http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir#2208c97c1bec2512d4e47b6223db6d95a7037956 [Hexagon,test] Change llc -march= to -mtriple=Similar to 806761a7629df268c8aed49657aeccffa6bca449-mtriple= specifies the full target triple while -march= merely sets thearchitecture part of the default target triple, leaving a target triple whichmay not make sense.Therefore, -march= is error-prone and not recommended for tests without a targettriple. The issue has been benign as we recognize $unknown-apple-darwin as ELF insteadof rejecting it outrightly. List of files: /llvm-project/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir Sun, 15 Dec 2024 18:20:22 +0000 Fangrui Song <i@maskray.me> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir#43e94b15ea0c180ebb0fd3e6b697dac4564aaf60 Followup on Proposal to move MIR physical register namespace to '$' sigil.Discussed here:http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.htmlIn preparation for adding support for named vregs we are changing the sigil forphysical registers in MIR to '$' from '%'. This will prevent name clashes ofnamed physical register with named vregs.llvm-svn: 323922 List of files: /llvm-project/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir Wed, 31 Jan 2018 22:04:26 +0000 Puyan Lotfi <puyan@puyan.org> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir#1a1edbfb048e83091bf6352e2be380d90976ed9b [Hexagon] Fix an incorrect assertion in HexagonConstExtendersllvm-svn: 323548 List of files: /llvm-project/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir Fri, 26 Jan 2018 19:20:50 +0000 Krzysztof Parzyszek <kparzysz@codeaurora.org>