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    <title>Changes in addrmode-align.ll</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>2208c97c1bec2512d4e47b6223db6d95a7037956 - [Hexagon,test] Change llc -march= to -mtriple=</title>
        <link>http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/addrmode-align.ll#2208c97c1bec2512d4e47b6223db6d95a7037956</link>
        <description>[Hexagon,test] Change llc -march= to -mtriple=Similar to 806761a7629df268c8aed49657aeccffa6bca449-mtriple= specifies the full target triple while -march= merely sets thearchitecture part of the default target triple, leaving a target triple whichmay not make sense.Therefore, -march= is error-prone and not recommended for tests without a targettriple. The issue has been benign as we recognize $unknown-apple-darwin as ELF insteadof rejecting it outrightly.

            List of files:
            /llvm-project/llvm/test/CodeGen/Hexagon/addrmode-align.ll</description>
        <pubDate>Sun, 15 Dec 2024 18:20:22 +0000</pubDate>
        <dc:creator>Fangrui Song &lt;i@maskray.me&gt;</dc:creator>
    </item>
<item>
        <title>a96f691985c8546e826012fdc3481c88f034a194 - [Hexagon] Convert some tests to opaque pointers (NFC)</title>
        <link>http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/addrmode-align.ll#a96f691985c8546e826012fdc3481c88f034a194</link>
        <description>[Hexagon] Convert some tests to opaque pointers (NFC)

            List of files:
            /llvm-project/llvm/test/CodeGen/Hexagon/addrmode-align.ll</description>
        <pubDate>Mon, 19 Dec 2022 11:52:45 +0000</pubDate>
        <dc:creator>Nikita Popov &lt;npopov@redhat.com&gt;</dc:creator>
    </item>
<item>
        <title>9897daa6bfcce044473f63e12492ec7748e8eb62 - Update LSR&apos;s logic that identifies a post-increment SCEV value.</title>
        <link>http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/addrmode-align.ll#9897daa6bfcce044473f63e12492ec7748e8eb62</link>
        <description>Update LSR&apos;s logic that identifies a post-increment SCEV value.One of the checks has been removed as it seem invalid.The LoopStep size is always almost a 32-bit.Differential Revision: https://reviews.llvm.org/D75079

            List of files:
            /llvm-project/llvm/test/CodeGen/Hexagon/addrmode-align.ll</description>
        <pubDate>Mon, 02 Mar 2020 22:32:19 +0000</pubDate>
        <dc:creator>Sumanth Gundapaneni &lt;sgundapa@quicinc.com&gt;</dc:creator>
    </item>
<item>
        <title>5488deb1ab2334fe2850e885a3b755a58143e992 - [Hexagon] Add more lit tests</title>
        <link>http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/Hexagon/addrmode-align.ll#5488deb1ab2334fe2850e885a3b755a58143e992</link>
        <description>[Hexagon] Add more lit testsllvm-svn: 328561

            List of files:
            /llvm-project/llvm/test/CodeGen/Hexagon/addrmode-align.ll</description>
        <pubDate>Mon, 26 Mar 2018 17:53:48 +0000</pubDate>
        <dc:creator>Krzysztof Parzyszek &lt;kparzysz@codeaurora.org&gt;</dc:creator>
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