en Copyright 2015 Java http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/AArch64/bf16-select.ll#61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9 Revert "[AArch64] Enable subreg liveness tracking by default."This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7.Some issues were discovered with the bootstrap builds, whichseem like they were caused by this commit. I'm reverting to investigate. List of files: /llvm-project/llvm/test/CodeGen/AArch64/bf16-select.ll Thu, 12 Dec 2024 17:19:43 +0000 Sander de Smalen <sander.desmalen@arm.com> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/AArch64/bf16-select.ll#9c319d5bb40785c969d2af76535ca62448dfafa7 [AArch64] Enable subreg liveness tracking by default.Internal testing didn't flag up any functional- or performance regressions. List of files: /llvm-project/llvm/test/CodeGen/AArch64/bf16-select.ll Tue, 15 Oct 2024 12:54:51 +0000 Sander de Smalen <sander.desmalen@arm.com> http://src.rcs.uwaterloo.ca:8080/source/history/llvm-project/llvm/test/CodeGen/AArch64/bf16-select.ll#a9e9dd9a3a44d88cda85d0b26778c80faf5355d2 [AArch64] Add bf16 select handlingA bfloat select operation will currently crash, but is allowed from C.This adds handling for the operation, turning it into a FCSELHrrr iffullfp16 is present, or converting it to a FCSELSrrr if not. TheFCSELSrrr is created via using INSERT_SUBREG/EXTRACT_SUBREG to convertthe bf16 to a f32 and using the f32 pattern for FCSELSrrr. (I originallyattempted to do this via a tablegen pattern, but it appears that thenzcv glue is places onto the wrong node, causing it to be forgotten andincorrect scheduling to be emitted).The FCSELSrrr can also be used for fp16 selects when +fullfp16 is notpresent, which helps avoid an unnecessary promotion to f32.Differential Revision: https://reviews.llvm.org/D131253 List of files: /llvm-project/llvm/test/CodeGen/AArch64/bf16-select.ll Thu, 11 Aug 2022 13:20:36 +0000 David Green <david.green@arm.com>