11 ifetch(ulong addr)  in ifetch()  argument
15 	if(addr&3) {  in ifetch()
16 		Bprint(bioout, "instruction_address_not_aligned [addr %.8lux]\n", addr);  in ifetch()
21 		updateicache(addr);  in ifetch()
23 	va = vaddr(addr);  in ifetch()
24 	iprof[(addr-textbase)/PROFGRAN]++;  in ifetch()
26 	va += addr&(BY2PG-1);  in ifetch()
32 getmem_4(ulong addr)  in getmem_4()  argument
39 		val = val<<8 | getmem_b(addr++);  in getmem_4()
44 getmem_2(ulong addr)  in getmem_2()  argument
48 	val = getmem_b(addr);  in getmem_2()
49 	val = val<<8 | getmem_b(addr+1);  in getmem_2()
55 getmem_w(ulong addr)  in getmem_w()  argument
59 	if(addr&3) {  in getmem_w()
60 		Bprint(bioout, "mem_address_not_aligned [load addr %.8lux]\n", addr);  in getmem_w()
64 		brkchk(addr, Read);  in getmem_w()
66 	va = vaddr(addr);  in getmem_w()
67 	va += addr&(BY2PG-1);  in getmem_w()
73 getmem_h(ulong addr)  in getmem_h()  argument
77 	if(addr&1) {  in getmem_h()
78 		Bprint(bioout, "mem_address_not_aligned [load addr %.8lux]\n", addr);  in getmem_h()
82 		brkchk(addr, Read);  in getmem_h()
84 	va = vaddr(addr);  in getmem_h()
85 	va += addr&(BY2PG-1);  in getmem_h()
91 getmem_b(ulong addr)  in getmem_b()  argument
96 		brkchk(addr, Read);  in getmem_b()
98 	va = vaddr(addr);  in getmem_b()
99 	va += addr&(BY2PG-1);  in getmem_b()
104 putmem_w(ulong addr, ulong data)  in putmem_w()  argument
108 	if(addr&3) {  in putmem_w()
109 		Bprint(bioout, "mem_address_not_aligned [store addr %.8lux]\n", addr);  in putmem_w()
113 	va = vaddr(addr);  in putmem_w()
114 	va += addr&(BY2PG-1);  in putmem_w()
121 		brkchk(addr, Write);  in putmem_w()
124 putmem_b(ulong addr, uchar data)  in putmem_b()  argument
128 	va = vaddr(addr);  in putmem_b()
129 	va += addr&(BY2PG-1);  in putmem_b()
132 		brkchk(addr, Write);  in putmem_b()
136 putmem_h(ulong addr, short data)  in putmem_h()  argument
140 	if(addr&1) {  in putmem_h()
141 		Bprint(bioout, "mem_address_not_aligned [store addr %.8lux]\n", addr);  in putmem_h()
145 	va = vaddr(addr);  in putmem_h()
146 	va += addr&(BY2PG-1);  in putmem_h()
150 		brkchk(addr, Write);  in putmem_h()
191 vaddr(ulong addr)  in vaddr()  argument
199 		if(addr >= s->base && addr < s->end) {  in vaddr()
201 			off = (addr-s->base)/BY2PG;  in vaddr()
237 	Bprint(bioout, "data_access_MMU_miss [addr 0x%.8lux]\n", addr);  in vaddr()