127 void		ural_write(struct ural_softc *, uint16_t, uint16_t);
536 			ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_task()
539 			ural_write(sc, RAL_MAC_CSR20, 0);  in ural_task()
592 		ural_write(sc, RAL_MAC_CSR20, 1);  in ural_task()
1404 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)  in ural_write()  function
1457 	ural_write(sc, RAL_PHY_CSR7, tmp);  in ural_bbp_write()
1467 	ural_write(sc, RAL_PHY_CSR7, val);  in ural_bbp_read()
1496 	ural_write(sc, RAL_PHY_CSR9,  tmp & 0xffff);  in ural_rf_write()
1497 	ural_write(sc, RAL_PHY_CSR10, tmp >> 16);  in ural_rf_write()
1620 	ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_enable_tsf_sync()
1623 	ural_write(sc, RAL_TXRX_CSR18, tmp);  in ural_enable_tsf_sync()
1636 	ural_write(sc, RAL_TXRX_CSR20, tmp);  in ural_enable_tsf_sync()
1646 	ural_write(sc, RAL_TXRX_CSR19, tmp);  in ural_enable_tsf_sync()
1672 	ural_write(sc, RAL_MAC_CSR10, slottime);  in ural_update_slot()
1673 	ural_write(sc, RAL_MAC_CSR11, sifs);  in ural_update_slot()
1674 	ural_write(sc, RAL_MAC_CSR12, eifs);  in ural_update_slot()
1688 	ural_write(sc, RAL_TXRX_CSR10, tmp);  in ural_set_txpreamble()
1699 		ural_write(sc, RAL_TXRX_CSR11, 0x3);  in ural_set_basicrates()
1702 		ural_write(sc, RAL_TXRX_CSR11, 0xf);  in ural_set_basicrates()
1712 	ural_write(sc, RAL_MAC_CSR5, tmp);  in ural_set_bssid()
1715 	ural_write(sc, RAL_MAC_CSR6, tmp);  in ural_set_bssid()
1718 	ural_write(sc, RAL_MAC_CSR7, tmp);  in ural_set_bssid()
1729 	ural_write(sc, RAL_MAC_CSR2, tmp);  in ural_set_macaddr()
1732 	ural_write(sc, RAL_MAC_CSR3, tmp);  in ural_set_macaddr()
1735 	ural_write(sc, RAL_MAC_CSR4, tmp);  in ural_set_macaddr()
1753 	ural_write(sc, RAL_TXRX_CSR2, tmp);  in ural_update_promisc()
1858 	ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));  in ural_set_txantenna()
1861 	ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));  in ural_set_txantenna()
1897 		ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);  in ural_init()
1915 	ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);  in ural_init()
1918 	ural_write(sc, RAL_TXRX_CSR11, 0x153);  in ural_init()
2020 	ural_write(sc, RAL_TXRX_CSR2, tmp);  in ural_init()
2050 	ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);  in ural_stop()
2053 	ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);  in ural_stop()
2054 	ural_write(sc, RAL_MAC_CSR1, 0);  in ural_stop()