38 dbdma_start(dbdma_regmap_t *dmap, dbdma_t dt)  in dbdma_start()  argument
42 	DBDMA_ST4_ENDIAN(&dmap->d_intselect, DBDMA_CLEAR_CNTRL((0xffff)));  in dbdma_start()
43 	DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_CLEAR_CNTRL((  in dbdma_start()
54 	} while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE);  in dbdma_start()
57 	DBDMA_ST4_ENDIAN(&dmap->d_cmdptrhi, 0); /* 64-bit not yet */  in dbdma_start()
58 	DBDMA_ST4_ENDIAN(&dmap->d_cmdptrlo, addr);  in dbdma_start()
60 	DBDMA_ST4_ENDIAN(&dmap->d_control,  in dbdma_start()
66 dbdma_stop(dbdma_regmap_t *dmap)  in dbdma_stop()  argument
68 	DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_RUN) |  in dbdma_stop()
71 	while (DBDMA_LD4_ENDIAN(&dmap->d_status) &  in dbdma_stop()
76 dbdma_flush(dbdma_regmap_t *dmap)  in dbdma_flush()  argument
78 	DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH));  in dbdma_flush()
81 	while (DBDMA_LD4_ENDIAN(&dmap->d_status) & (DBDMA_CNTRL_FLUSH));  in dbdma_flush()
85 dbdma_reset(dbdma_regmap_t *dmap)  in dbdma_reset()  argument
87 	DBDMA_ST4_ENDIAN(&dmap->d_control,  in dbdma_reset()
96 	while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_RUN);  in dbdma_reset()
100 dbdma_continue(dbdma_regmap_t *dmap)  in dbdma_continue()  argument
102 	DBDMA_ST4_ENDIAN(&dmap->d_control,  in dbdma_continue()
108 dbdma_pause(dbdma_regmap_t *dmap)  in dbdma_pause()  argument
110 	DBDMA_ST4_ENDIAN(&dmap->d_control,DBDMA_SET_CNTRL(DBDMA_CNTRL_PAUSE));  in dbdma_pause()
113 	while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE);  in dbdma_pause()