Lines Matching refs:RB
396 #define RB RAOPT + 1 macro
403 #define RBS RB + 1
1860 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1861 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1862 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1863 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1864 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1865 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1866 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1867 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1868 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1869 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1870 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1871 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1872 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1873 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1874 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1875 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1876 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1891 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1892 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1893 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1894 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1895 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1896 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1897 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1898 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1899 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1900 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1901 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1902 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1903 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1904 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1905 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1906 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1907 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1908 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1909 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1910 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1911 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1912 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1913 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1914 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1915 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1916 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1917 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1918 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1919 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1920 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1921 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1922 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1923 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1924 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1925 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1926 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1927 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1928 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1929 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1930 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1931 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1932 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1933 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1934 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1935 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2102 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2103 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2104 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2105 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2106 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2107 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2116 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2118 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2119 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2121 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2122 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2123 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2124 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2125 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2127 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2129 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2131 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2133 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2134 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2139 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2140 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2141 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2142 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2144 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2145 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2146 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2147 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2148 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2149 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2152 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2154 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2156 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2158 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2160 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2162 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2164 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2166 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2168 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2170 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2172 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2175 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2177 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2179 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2181 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2183 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2185 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2187 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2192 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2193 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2194 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2195 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2196 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2197 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2198 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2199 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2200 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2201 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2202 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2203 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2204 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2205 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2206 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2207 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2208 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2209 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2210 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2211 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2216 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2217 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2218 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2219 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2220 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2221 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2222 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2223 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2224 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2225 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2226 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2227 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2228 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2229 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2230 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2231 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2232 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2233 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2234 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2235 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2237 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2238 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2239 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2240 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2241 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2242 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2243 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2244 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2245 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2246 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2247 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2248 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2249 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2250 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2251 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2252 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2254 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2255 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2256 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2257 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2258 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2259 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2260 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2261 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2262 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2263 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2264 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2265 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2268 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2269 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2270 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2271 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2272 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2273 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2274 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2275 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2276 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2277 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2281 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2283 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2285 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2287 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2288 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2289 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2290 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2294 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2295 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2296 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2297 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2299 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2301 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2303 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2307 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2308 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2309 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2311 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2312 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2314 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2318 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2319 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2320 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2326 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2330 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2331 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2332 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2333 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2348 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
3094 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3095 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3102 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3103 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3104 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3105 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3106 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3107 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3144 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3145 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3146 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3147 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3149 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3150 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3152 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3153 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3154 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3155 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3157 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3158 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3159 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3160 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3161 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3162 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3163 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3164 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3165 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3166 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3167 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3168 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3169 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3170 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3171 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3172 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3173 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3174 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3175 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3176 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3177 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3178 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3179 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3180 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3181 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3182 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3183 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3184 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3186 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3187 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3189 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3190 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3191 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3192 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3193 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3194 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3195 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3196 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3197 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3198 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3199 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3200 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3202 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3203 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3205 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3206 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3207 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3208 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3209 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3210 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3211 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3212 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3214 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3215 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3217 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3218 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3219 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3220 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3225 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
3227 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3229 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3230 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3232 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3233 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3235 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3236 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3237 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3238 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3245 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3246 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3248 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3249 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3251 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3252 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3254 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3256 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3258 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3259 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3260 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3261 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3263 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3264 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3265 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3266 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3267 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3268 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3269 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3270 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3272 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3274 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3276 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3277 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3279 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3281 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3286 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3287 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3289 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3290 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3291 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3292 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3293 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3294 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3295 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3296 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3297 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3298 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3299 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3300 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3301 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3302 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3303 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3305 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3306 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3308 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3309 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3311 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3312 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3318 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
3320 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3322 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3324 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3326 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3333 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3334 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3335 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3336 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3338 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3340 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3342 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3345 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3347 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3349 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3351 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3355 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3357 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3358 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3359 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3360 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3361 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3362 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3363 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3364 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3366 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3367 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3368 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3369 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3370 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3371 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3372 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3373 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3375 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3382 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3384 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3386 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3387 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3389 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3391 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3393 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3394 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3396 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3397 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3401 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3402 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3406 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3408 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3409 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3414 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3436 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3438 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3440 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3441 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3443 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3444 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3446 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3448 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3459 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3460 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3461 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3462 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3473 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3474 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3475 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3476 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3477 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3478 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3479 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3480 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3482 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3483 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3484 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3486 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3488 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3493 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3495 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3499 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3500 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3501 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3502 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3504 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3505 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3506 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3507 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3508 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3509 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3510 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3511 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3513 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3517 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3518 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3520 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3522 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3524 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3525 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3527 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3529 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3531 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3532 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3534 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3536 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3538 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3539 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3541 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3579 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3580 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3581 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3582 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3778 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3780 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3781 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3783 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3785 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3787 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3788 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3790 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3797 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3798 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3799 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3800 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3804 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3806 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3808 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3812 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3814 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3815 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3817 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3818 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3820 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3822 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3824 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3826 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3828 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3830 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3832 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3834 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3835 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3840 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3842 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3844 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3846 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3848 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3851 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3853 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3894 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3895 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3896 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3897 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3902 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3903 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3904 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3905 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4060 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4062 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4063 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4065 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4067 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4071 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4080 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4081 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4082 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4083 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4088 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4089 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4090 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4091 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4093 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4099 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4108 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4109 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4111 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4112 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4114 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4116 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4117 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4118 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4119 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4121 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4122 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4124 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4125 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4127 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4128 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4130 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4132 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4138 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4140 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4153 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4155 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4157 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4161 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4163 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4165 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4167 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4168 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4170 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4171 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4173 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4175 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4176 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4178 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4179 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4181 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4183 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4185 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4190 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4195 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4197 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4198 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4200 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4201 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4203 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4205 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4207 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4212 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4214 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4216 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4217 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4219 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4221 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4222 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4223 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4224 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4226 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4227 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4229 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4231 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4232 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4234 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4244 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4249 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4250 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4251 { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4252 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4253 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4254 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4256 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4258 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4260 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4261 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4263 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4264 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4271 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4273 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4286 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4288 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4293 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4295 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4297 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4302 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4304 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4305 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4307 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4309 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4310 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4311 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4313 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4315 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4316 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4317 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4318 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4319 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4320 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4321 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4322 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4323 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4324 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4325 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4326 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },