Lines Matching refs:FP
70 #define FP (NoSuf) macro
598 {"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
605 {"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
606 {"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
610 {"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
616 {"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
623 {"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
624 {"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
628 {"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
630 {"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} },
633 {"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
635 {"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} },
641 {"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
643 {"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} },
647 {"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} },
650 {"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
652 {"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} },
653 {"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
655 {"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} },
656 {"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} },
658 {"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} },
659 {"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} },
662 {"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} },
663 {"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} },
664 {"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} },
665 {"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} },
666 {"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} },
667 {"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} },
668 {"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} },
673 {"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
675 {"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
678 {"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} },
683 {"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
684 {"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
686 {"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} },
687 {"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
690 {"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
691 {"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
694 {"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },
700 {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
701 {"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
702 {"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
704 {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
707 {"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
708 {"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
709 {"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
713 {"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
714 {"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
717 {"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },
723 {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
724 {"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
725 {"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
727 {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
730 {"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
731 {"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
732 {"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
736 {"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
737 {"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
740 {"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },
745 {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
746 {"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
747 {"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} },
748 {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
751 {"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
752 {"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
755 {"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },
761 {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
762 {"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
763 {"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
765 {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
768 {"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
769 {"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
770 {"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
774 {"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
775 {"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
778 {"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },
784 {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
785 {"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
786 {"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
788 {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
791 {"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
792 {"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
793 {"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
796 {"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} },
797 {"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} },
798 {"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} },
799 {"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} },
800 {"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} },
801 {"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} },
802 {"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} },
803 {"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} },
804 {"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} },
805 {"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} },
806 {"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} },
807 {"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} },
808 {"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} },
809 {"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} },
810 {"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} },
811 {"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} },
812 {"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} },
813 {"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} },
816 {"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} },
817 {"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} },
822 {"fnstsw", 1, 0xdfe0, X, 0, FP|IgnoreSize, { Acc, 0, 0} },
824 {"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} },
826 {"fstsw", 1, 0xdfe0, X, 0, FP|FWait|IgnoreSize, { Acc, 0, 0} },
828 {"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} },
829 {"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} },
830 {"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} },
839 {"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
841 {"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
842 {"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} },
844 {"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} },
959 {"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
960 {"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
961 {"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
962 {"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
963 {"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
964 {"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
965 {"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
966 {"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
967 {"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
968 {"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
969 {"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
970 {"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
972 {"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
973 {"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
974 {"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
975 {"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
976 {"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
977 {"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
978 {"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
979 {"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
980 {"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
981 {"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
982 {"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
983 {"fucomip", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
984 {"fucomip", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
985 {"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
986 {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
987 {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
995 {"rdfsbase", 1, 0xf30fae, 0, CpuNEW, FP|Modrm, { Reg32|Reg64, 0, 0 } },
996 {"rdgsbase", 1, 0xf30fae, 1, CpuNEW, FP|Modrm, { Reg32|Reg64, 0, 0 } },
997 {"wrfsbase", 1, 0xf30fae, 2, CpuNEW, FP|Modrm, { Reg32|Reg64, 0, 0 } },
998 {"wrgsbase", 1, 0xf30fae, 3, CpuNEW, FP|Modrm, { Reg32|Reg64, 0, 0 } },
1348 {"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} },
1504 {"aesdec", 2, 0x660f38de, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } },
1505 {"aesdeclast", 2, 0x660f38df, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } },
1506 {"aesenc", 2, 0x660f38dc, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } },
1507 {"aesenclast", 2, 0x660f38dd, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } },
1508 {"aesimc", 2, 0x660f38db, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } },
1509 {"aeskeygenassist", 3, 0x660f3adf, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM|LLongMem, R…
1512 {"pclmulqdq", 3, 0x660f3a44, X, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM|LLongMem, RegX…
1513 {"pclmullqlqdq", 2, 0x660f3a44, 0x0, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem…
1514 {"pclmulhqlqdq", 2, 0x660f3a44, 0x1, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem…
1515 {"pclmullqhqdq", 2, 0x660f3a44, 0x10, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMe…
1516 {"pclmulhqhqdq", 2, 0x660f3a44, 0x11, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMe…
1558 #undef FP