Lines Matching refs:getOpcode
266 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
271 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
671 switch (StoreVal.getOpcode()) { in getStoreSource()
914 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
922 (N.getOpcode() == ISD::STRICT_FSETCC || in isSetCCEquivalent()
923 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
930 if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) || in isSetCCEquivalent()
987 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
1004 if (V.getOpcode() != ISD::BUILD_VECTOR) in isAnyConstantBuildVector()
1013 (LD->getOperand(2).getOpcode() != ISD::TargetConstant || in canSplitIdx()
1031 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD) in reassociationCanBreakAddressingModePattern()
1074 if (GA->getOpcode() == ISD::GlobalAddress && TLI.isOffsetFoldingLegal(GA)) in reassociationCanBreakAddressingModePattern()
1105 if (N0.getOpcode() != Opc) in reassociateOpsCommutative()
1300 unsigned Opc = Op.getOpcode(); in PromoteOperand()
1367 unsigned Opc = Op.getOpcode(); in PromoteIntBinOp()
1435 unsigned Opc = Op.getOpcode(); in PromoteIntShiftOp()
1468 if (Op && Op.getOpcode() != ISD::DELETED_NODE) in PromoteIntShiftOp()
1484 unsigned Opc = Op.getOpcode(); in PromoteExtend()
1497 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); in PromoteExtend()
1515 unsigned Opc = Op.getOpcode(); in PromoteLoad()
1649 assert(N->getOpcode() != ISD::DELETED_NODE && in Run()
1650 RV.getOpcode() != ISD::DELETED_NODE && in Run()
1668 if (RV.getOpcode() != ISD::EntryToken) { in Run()
1686 switch (N->getOpcode()) { in visit()
1842 assert(N->getOpcode() != ISD::DELETED_NODE && in combine()
1845 if (N->getOpcode() >= ISD::BUILTIN_OP_END || in combine()
1846 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { in combine()
1858 switch (N->getOpcode()) { in combine()
1887 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode())) { in combine()
1894 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops, in combine()
1940 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor) in visitTokenFactor()
1969 switch (Op.getOpcode()) { in visitTokenFactor()
2055 switch (CurNode->getOpcode()) { in visitTokenFactor()
2166 if (N->getOpcode() == ISD::ADD) { in canFoldInAddressingMode()
2175 } else if (N->getOpcode() == ISD::SUB) { in canFoldInAddressingMode()
2206 if (N1.getOpcode() != ISD::VSELECT || !N1.hasOneUse()) in foldSelectWithIdentityConstant()
2210 unsigned Opcode = N->getOpcode(); in foldSelectWithIdentityConstant()
2238 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && in foldBinOpIntoSelect()
2242 auto BinOpcode = BO->getOpcode(); in foldBinOpIntoSelect()
2248 if (TLI.isCommutativeBinOp(BO->getOpcode())) in foldBinOpIntoSelect()
2258 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) { in foldBinOpIntoSelect()
2263 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) in foldBinOpIntoSelect()
2334 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubBoolOfMaskedVal()
2340 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubBoolOfMaskedVal()
2344 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
2348 if (Z.getOperand(0).getOpcode() != ISD::SETCC || in foldAddSubBoolOfMaskedVal()
2356 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
2375 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubOfSignBit()
2380 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubOfSignBit()
2384 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2415 unsigned Opcode = V.getOpcode(); in isADDLike()
2461 if (N0.getOpcode() == ISD::SUB) { in visitADDLike()
2478 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && in visitADDLike()
2527 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0))) in visitADDLike()
2531 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitADDLike()
2535 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) in visitADDLike()
2539 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) in visitADDLike()
2543 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2549 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2555 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADDLike()
2561 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADDLike()
2567 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && in visitADDLike()
2568 N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLike()
2570 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0), in visitADDLike()
2574 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2588 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { in visitADDLike()
2609 if (N0.getOpcode() == ISD::ADD) { in visitADDLike()
2628 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && in visitADDLike()
2637 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitADDLike()
2673 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2680 if (N0.getOpcode() == ISD::ADD && in visitADD()
2681 N0.getOperand(1).getOpcode() == ISD::VSCALE && in visitADD()
2682 N1.getOpcode() == ISD::VSCALE) { in visitADD()
2690 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitADD()
2691 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD()
2699 if (N0.getOpcode() == ISD::ADD && in visitADD()
2700 N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR && in visitADD()
2701 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD()
2713 unsigned Opcode = N->getOpcode(); in visitADDSAT()
2759 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
2764 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) { in getAsCarry()
2777 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY && in getAsCarry()
2778 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO) in getAsCarry()
2782 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT)) in getAsCarry()
2801 if (N1.getOpcode() == ISD::ZERO_EXTEND) in foldAddSubMasked1()
2804 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1))) in foldAddSubMasked1()
2809 if (N10.getValueType() != VT && N10.getOpcode() == ISD::TRUNCATE) in foldAddSubMasked1()
2830 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLikeCommutative()
2844 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && in visitADDLikeCommutative()
2851 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) { in visitADDLikeCommutative()
2870 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADDLikeCommutative()
2878 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADDLikeCommutative()
2888 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) && in visitADDLikeCommutative()
2946 if (V.getOpcode() != ISD::XOR) in extractBooleanFlip()
2979 bool IsSigned = (ISD::SADDO == N->getOpcode()); in visitADDO()
2992 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitADDO()
3029 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) { in visitUADDOLike()
3059 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitADDE()
3164 if (Carry1.getOpcode() != ISD::UADDO) in combineADDCARRYDiamond()
3173 if (Carry0.getOpcode() == ISD::ADDCARRY && in combineADDCARRYDiamond()
3176 } else if (Carry0.getOpcode() == ISD::UADDO && in combineADDCARRYDiamond()
3259 unsigned Opcode = Carry0.getOpcode(); in combineCarryDiamond()
3260 if (Opcode != Carry1.getOpcode()) in combineCarryDiamond()
3288 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND) in combineCarryDiamond()
3313 if (N->getOpcode() == ISD::AND) in combineCarryDiamond()
3334 if ((N0.getOpcode() == ISD::ADD || in visitADDCARRYLike()
3335 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && in visitADDCARRYLike()
3388 if (N->getOpcode() != ISD::SUB || in foldSubToUSubSat()
3398 if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in foldSubToUSubSat()
3407 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { in foldSubToUSubSat()
3417 if (Op1.getOpcode() == ISD::TRUNCATE && in foldSubToUSubSat()
3418 Op1.getOperand(0).getOpcode() == ISD::UMIN && in foldSubToUSubSat()
3422 if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0) in foldSubToUSubSat()
3425 if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0) in foldSubToUSubSat()
3451 if (N->getOpcode() == ISD::FREEZE && N.hasOneUse()) in visitSUB()
3492 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3495 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3516 if (N1.getOpcode() == ISD::ABS && N1.hasOneUse() && in visitSUB()
3524 if (N1S && N1S.getOpcode() == ISD::SUB && in visitSUB()
3535 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitSUB()
3539 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) in visitSUB()
3543 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) in visitSUB()
3547 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) in visitSUB()
3551 if (N0.getOpcode() == ISD::ADD) { in visitSUB()
3558 if (N1.getOpcode() == ISD::ADD) { in visitSUB()
3565 if (N0.getOpcode() == ISD::SUB) { in visitSUB()
3572 if (N0.getOpcode() == ISD::SUB) { in visitSUB()
3579 if (N0.getOpcode() == ISD::ADD && in visitSUB()
3580 (N0.getOperand(1).getOpcode() == ISD::SUB || in visitSUB()
3581 N0.getOperand(1).getOpcode() == ISD::ADD) && in visitSUB()
3583 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0), in visitSUB()
3587 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD && in visitSUB()
3593 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
3599 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse()) in visitSUB()
3605 if (N1.getOpcode() == ISD::AND) { in visitSUB()
3619 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) { in visitSUB()
3620 if (N1.getOperand(0).getOpcode() == ISD::SUB && in visitSUB()
3627 if (N1.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
3655 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && isOneOrOneSplat(N1)) { in visitSUB()
3672 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && in visitSUB()
3678 if (N1.getOpcode() == ISD::ADD && N1.hasOneUse() && in visitSUB()
3685 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSUB()
3691 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSUB()
3700 if (N1.getOpcode() == ISD::ZERO_EXTEND && in visitSUB()
3710 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { in visitSUB()
3724 if (N1C && GA->getOpcode() == ISD::GlobalAddress) in visitSUB()
3736 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
3746 if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) { in visitSUB()
3752 if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) { in visitSUB()
3760 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
3773 if (N1.getOpcode() == ISD::SHL) { in visitSUB()
3780 if (N0.getOpcode() == ISD::SUBCARRY && isNullConstant(N0.getOperand(1)) && in visitSUB()
3810 if (N0.getOpcode() != Max || N1.getOpcode() != Min) in visitSUB()
3844 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1})) in visitSUBSAT()
3896 bool IsSigned = (ISD::SSUBO == N->getOpcode()); in visitSUBO()
3937 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitSUBE()
3988 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale); in visitMULFIX()
4138 if (N0.getOpcode() == ISD::SHL) { in visitMUL()
4150 if (N0.getOpcode() == ISD::SHL && in visitMUL()
4153 } else if (N1.getOpcode() == ISD::SHL && in visitMUL()
4167 N0.getOpcode() == ISD::ADD && in visitMUL()
4177 if (N0.getOpcode() == ISD::VSCALE && NC1) { in visitMUL()
4185 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitMUL()
4210 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"); in visitMUL()
4257 unsigned Opcode = Node->getOpcode(); in useDivRem()
4291 if (User == Node || User->getOpcode() == ISD::DELETED_NODE || in useDivRem()
4297 unsigned UserOpc = User->getOpcode(); in useDivRem()
4327 unsigned Opc = N->getOpcode(); in simplifyDivRem()
4587 if (N1.getOpcode() == ISD::SHL) { in visitUDIVLike()
4625 unsigned Opcode = N->getOpcode(); in visitREM()
4670 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && in visitREM()
4855 unsigned Opcode = N->getOpcode(); in visitAVG()
4926 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
4936 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
5035 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
5058 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitMULO()
5116 if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) in isSaturatingMinMax()
5137 switch (N0.getOpcode()) { in isSaturatingMinMax()
5142 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; in isSaturatingMinMax()
5153 if (N0.getOperand(0).getOpcode() != ISD::SETCC) in isSaturatingMinMax()
5198 if (!Fp || Fp.getOpcode() != ISD::FP_TO_SINT) in PerformMinMaxFpToSatCombine()
5222 (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) || in PerformUMinFpToSatCombine()
5223 N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT) in PerformUMinFpToSatCombine()
5255 unsigned Opcode = N->getOpcode(); in visitIMINMAX()
5313 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands()
5314 unsigned HandOpcode = N0.getOpcode(); in hoistLogicOpWithSameOpcodeHands()
5317 assert(HandOpcode == N1.getOpcode() && "Bad input!"); in hoistLogicOpWithSameOpcodeHands()
5648 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
5683 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in visitANDLike()
5870 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) && in SearchForAndLoads()
5879 switch(Op.getOpcode()) { in SearchForAndLoads()
5903 EVT VT = Op.getOpcode() == ISD::AssertZext ? in SearchForAndLoads()
5976 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
6000 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
6020 assert(N->getOpcode() == ISD::AND); in unfoldExtremeBitClearingToShifts()
6036 OuterShift = M->getOpcode(); in unfoldExtremeBitClearingToShifts()
6072 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op"); in combineShiftAnd1ToBitTest()
6082 if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) in combineShiftAnd1ToBitTest()
6099 if (Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6104 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6152 if (N0.getOpcode() == ISD::SRA) in foldAndToUsubsat()
6156 if (N0.getOpcode() != ISD::XOR && N0.getOpcode() != ISD::ADD) in foldAndToUsubsat()
6159 if (N1.getOpcode() != ISD::SRA || !N0.hasOneUse() || !N1.hasOneUse() || in foldAndToUsubsat()
6183 unsigned LogicOpcode = N->getOpcode(); in foldLogicOfShifts()
6192 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts()
6193 if (LogicOp.getOpcode() != LogicOpcode || in foldLogicOfShifts()
6205 if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6209 } else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6232 unsigned LogicOpcode = N->getOpcode(); in foldLogicTreeOfShifts()
6235 if (LeftHand.getOpcode() != LogicOpcode || in foldLogicTreeOfShifts()
6236 RightHand.getOpcode() != LogicOpcode) in foldLogicTreeOfShifts()
6344 if (N0.getOpcode() == ISD::OR && in visitAND()
6349 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
6358 if (ISD::isExtOpcode(N0.getOpcode())) { in visitAND()
6359 unsigned ExtOpc = N0.getOpcode(); in visitAND()
6361 if (N0Op0.getOpcode() == ISD::AND && in visitAND()
6382 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
6384 N0.getOperand(0).getOpcode() == ISD::LOAD && in visitAND()
6386 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND()
6387 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? in visitAND()
6489 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && in visitAND()
6490 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { in visitAND()
6532 if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector()) in visitAND()
6549 if (N0.getOpcode() == N1.getOpcode()) in visitAND()
6565 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { in visitAND()
6568 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && in visitAND()
6571 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && in visitAND()
6607 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { in visitAND()
6626 if (LHS->getOpcode() != ISD::SIGN_EXTEND) in visitAND()
6672 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
6674 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
6676 if (N0.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6689 if (N1.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6699 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
6701 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
6715 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6726 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
6784 unsigned Opc = N.getOpcode(); in isBSwapHWordElement()
6789 unsigned Opc0 = N0.getOpcode(); in isBSwapHWordElement()
6866 if (N.getOpcode() == ISD::OR) in isBSwapHWordPair()
6870 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { in isBSwapHWordPair()
6888 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 && in matchBSwapHWordOrAndAnd()
6892 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND) in matchBSwapHWordOrAndAnd()
6906 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
6959 } else if (N0.getOpcode() == ISD::OR) { in MatchBSwapHWord()
7006 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in visitORLike()
7032 if (N0.getOpcode() == ISD::AND && in visitORLike()
7033 N1.getOpcode() == ISD::AND && in visitORLike()
7049 if (N0.getOpcode() == ISD::AND) { in visitORCommutative()
7069 if (N0.getOpcode() == ISD::XOR) { in visitORCommutative()
7079 if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { in visitORCommutative()
7091 if (V->getOpcode() == ISD::ZERO_EXTEND) in visitORCommutative()
7097 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative()
7103 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
7239 if (N0.getOpcode() == ISD::AND && N0->hasOneUse() && in visitOR()
7255 if (N0.getOpcode() == N1.getOpcode()) in visitOR()
7287 if (Op.getOpcode() == ISD::AND && in stripConstantMask()
7299 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
7334 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) in extractShiftForRotate()
7348 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && in extractShiftForRotate()
7349 ExtractFrom.getOpcode() == ISD::ADD && in extractShiftForRotate()
7365 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant; in extractShiftForRotate()
7366 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift) in extractShiftForRotate()
7373 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
7374 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
7379 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || in extractShiftForRotate()
7502 if (Neg.getOpcode() != ISD::SUB) in matchRotateSub()
7537 (NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0))) in matchRotateSub()
7549 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) { in matchRotateSub()
7622 if (Op.getOpcode() != BinOpc) in MatchFunnelPosNeg()
7649 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) && in MatchFunnelPosNeg()
7688 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && in MatchRotate()
7734 if (LHSShift.getOpcode() == RHSShift.getOpcode()) in MatchRotate()
7738 if (RHSShift.getOpcode() == ISD::SHL) { in MatchRotate()
7745 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) in MatchRotate()
7791 if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR) in MatchRotate()
7860 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
7861 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
7862 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
7863 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && in MatchRotate()
7864 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
7865 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
7866 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
7867 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { in MatchRotate()
7990 (Op.getOpcode() != ISD::LOAD || !Op.getValueType().isVector())) in calculateByteProvider()
7995 if (Op.getOpcode() != ISD::LOAD && VectorIndex.has_value()) in calculateByteProvider()
8005 switch (Op.getOpcode()) { in calculateByteProvider()
8051 return Op.getOpcode() == ISD::ZERO_EXTEND in calculateByteProvider()
8146 switch (Value.getOpcode()) { in stripTruncAndExt()
8235 if (Trunc.getOpcode() != ISD::TRUNCATE) in mergeTruncStores()
8241 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && in mergeTruncStores()
8390 assert(N->getOpcode() == ISD::OR && in MatchLoadCombine()
8590 assert(N->getOpcode() == ISD::XOR); in unfoldMaskedMerge()
8602 if (And.getOpcode() != ISD::AND || !And.hasOneUse()) in unfoldMaskedMerge()
8605 if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse()) in unfoldMaskedMerge()
8731 unsigned N0Opcode = N0.getOpcode(); in visitXOR()
8805 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB && in visitXOR()
8812 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && in visitXOR()
8829 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) { in visitXOR()
8868 if (N0Opcode == N1.getOpcode()) in visitXOR()
8903 unsigned LogicOpcode = LogicOp.getOpcode(); in combineShiftOfShiftedLogic()
8909 unsigned ShiftOpcode = Shift->getOpcode(); in combineShiftOfShiftedLogic()
8916 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) in combineShiftOfShiftedLogic()
8985 switch (LHS.getOpcode()) { in visitShiftByConstant()
8993 if (N->getOpcode() != ISD::SHL) in visitShiftByConstant()
9002 bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL || in visitShiftByConstant()
9003 BinOpLHSVal.getOpcode() == ISD::SRA || in visitShiftByConstant()
9004 BinOpLHSVal.getOpcode() == ISD::SRL) && in visitShiftByConstant()
9006 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
9007 BinOpLHSVal.getOpcode() == ISD::SELECT; in visitShiftByConstant()
9019 N->getOpcode(), DL, VT, {LHS.getOperand(1), N->getOperand(1)})) { in visitShiftByConstant()
9020 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant()
9022 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
9029 assert(N->getOpcode() == ISD::TRUNCATE); in distributeTruncateThroughAnd()
9030 assert(N->getOperand(0).getOpcode() == ISD::AND); in distributeTruncateThroughAnd()
9080 return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt); in visitRotate()
9094 if (N1.getOpcode() == ISD::TRUNCATE && in visitRotate()
9095 N1.getOperand(0).getOpcode() == ISD::AND) { in visitRotate()
9097 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1); in visitRotate()
9100 unsigned NextOp = N0.getOpcode(); in visitRotate()
9109 bool SameSide = (N->getOpcode() == NextOp); in visitRotate()
9123 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0), in visitRotate()
9154 if (N0.getOpcode() == ISD::AND) { in visitSHL()
9159 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
9178 if (N1.getOpcode() == ISD::TRUNCATE && in visitSHL()
9179 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSHL()
9188 if (N0.getOpcode() == ISD::SHL) { in visitSHL()
9218 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in visitSHL()
9219 N0.getOpcode() == ISD::ANY_EXTEND || in visitSHL()
9220 N0.getOpcode() == ISD::SIGN_EXTEND) && in visitSHL()
9221 N0.getOperand(0).getOpcode() == ISD::SHL) { in visitSHL()
9252 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0)); in visitSHL()
9262 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && in visitSHL()
9263 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
9285 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { in visitSHL()
9311 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff); in visitSHL()
9319 if (N0.getOpcode() == ISD::SRL && in visitSHL()
9347 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) && in visitSHL()
9359 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) && in visitSHL()
9368 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1); in visitSHL()
9372 if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) { in visitSHL()
9385 if (N0.getOpcode() == ISD::VSCALE && N1C) { in visitSHL()
9393 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitSHL()
9411 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && in combineShiftToMULH()
9424 if (ShiftOperand.getOpcode() != ISD::MUL) in combineShiftToMULH()
9431 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH()
9432 bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND; in combineShiftToMULH()
9442 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) { in combineShiftToMULH()
9473 if (LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH()
9508 return (N->getOpcode() == ISD::SRA ? DAG.getSExtOrTrunc(Result, DL, WideVT) in combineShiftToMULH()
9542 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { in visitSRA()
9561 if (N0.getOpcode() == ISD::SRA) { in visitSRA()
9579 if (N1.getOpcode() == ISD::BUILD_VECTOR) in visitSRA()
9581 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
9597 if (N0.getOpcode() == ISD::SHL && N1C) { in visitSRA()
9637 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C && in visitSRA()
9639 bool IsAdd = N0.getOpcode() == ISD::ADD; in visitSRA()
9641 if (Shl.getOpcode() == ISD::SHL && Shl.getOperand(1) == N1 && in visitSRA()
9678 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRA()
9679 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRA()
9688 if (N0.getOpcode() == ISD::TRUNCATE && in visitSRA()
9689 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
9690 N0.getOperand(0).getOpcode() == ISD::SRA) && in visitSRA()
9763 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
9788 if (N1C && N0.getOpcode() == ISD::TRUNCATE && in visitSRL()
9789 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
9828 if (N0.getOpcode() == ISD::SHL && in visitSRL()
9865 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitSRL()
9891 if (N0.getOpcode() == ISD::SRA) in visitSRL()
9896 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
9933 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRL()
9934 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRL()
9980 if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) in visitSRL()
9983 if (Use->getOpcode() == ISD::BRCOND || Use->getOpcode() == ISD::AND || in visitSRL()
9984 Use->getOpcode() == ISD::OR || Use->getOpcode() == ISD::XOR) in visitSRL()
10001 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
10022 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1, in visitFunnelShift()
10120 DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0, N1})) in visitSHLSAT()
10127 if (N->getOpcode() == ISD::SSHLSAT && N1C && in visitSHLSAT()
10132 if (N->getOpcode() == ISD::USHLSAT && N1C && in visitSHLSAT()
10149 if (AbsOp1.getOpcode() != ISD::SUB) in foldABSToABD()
10155 unsigned Opc0 = Op0.getOpcode(); in foldABSToABD()
10157 if (Opc0 != Op1.getOpcode() || in foldABSToABD()
10196 if (N0.getOpcode() == ISD::ABS) in visitABS()
10207 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitABS()
10232 if (N0.getOpcode() == ISD::BSWAP) in visitBSWAP()
10239 if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) { in visitBSWAP()
10247 if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) { in visitBSWAP()
10269 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitBSWAP()
10275 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; in visitBSWAP()
10291 if (N0.getOpcode() == ISD::BITREVERSE) in visitBITREVERSE()
10469 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || in foldSelectOfConstantsUsingSra()
10501 if (Cond.getOpcode() != ISD::SETCC || !Cond->hasOneUse()) in shouldConvertSelectOfConstantsToMath()
10635 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && in foldBoolSelectToLogic()
10673 if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse()) in foldVSelectToSignBitSplatMask()
10768 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { in visitSELECT()
10781 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) { in visitSELECT()
10795 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) { in visitSELECT()
10814 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) { in visitSELECT()
10834 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
10854 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) { in visitSELECT()
10908 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
10909 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
10910 Cond.getOpcode() == ISD::BUILD_VECTOR); in ConvertSelectToConcatVector()
10956 if (Index.getOpcode() != ISD::ADD) in refineUniformBase()
10994 if (Index.getOpcode() == ISD::ZERO_EXTEND) { in refineIndexType()
11008 if (Index.getOpcode() == ISD::SIGN_EXTEND && in refineIndexType()
11123 if (N->getOpcode() != ISD::DELETED_NODE) in visitMSTORE()
11133 if ((Value.getOpcode() == ISD::TRUNCATE) && Value->hasOneUse() && in visitMSTORE()
11322 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
11330 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) in visitVSELECT()
11333 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) in visitVSELECT()
11378 if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() && in visitVSELECT()
11408 if (Other && Other.getOpcode() == ISD::ADD) { in visitVSELECT()
11425 if (OpRHS.getOpcode() == CondRHS.getOpcode() && in visitVSELECT()
11426 (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
11427 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
11459 if (Other && Other.getOpcode() == ISD::TRUNCATE && in visitVSELECT()
11460 Other.getOperand(0).getOpcode() == ISD::SUB && in visitVSELECT()
11464 if (LHS == OpLHS && RHS == OpRHS && LHS.getOpcode() == ISD::ZERO_EXTEND) in visitVSELECT()
11479 Other.getOpcode() == ISD::SUB && OpRHS == CondRHS) in visitVSELECT()
11482 if (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
11483 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
11484 if (CondRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
11485 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
11494 if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD && in visitVSELECT()
11507 if (SatCC == ISD::SETLT && Other.getOpcode() == ISD::XOR && in visitVSELECT()
11536 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
11537 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
11589 if (SCC.getOpcode() == ISD::SETCC) { in visitSELECT_CC()
11611 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; in visitSETCC()
11649 if (N0->getOpcode() == ISD::FREEZE && N0.hasOneUse() && N1C) { in visitSETCC()
11655 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse() && N0C) { in visitSETCC()
11675 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) { in visitSETCC()
11738 unsigned Opcode = N->getOpcode(); in tryToFoldExtendSelectLoad()
11747 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
11781 unsigned Opcode = N->getOpcode(); in tryToFoldExtendOfConstant()
11802 if (N0->getOpcode() == ISD::SELECT) { in tryToFoldExtendOfConstant()
11880 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
11903 if (User->getOpcode() == ISD::CopyToReg) in ExtendUsesToFormExtLoad()
11912 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
11952 assert((N->getOpcode() == ISD::SIGN_EXTEND || in CombineExtLoad()
11953 N->getOpcode() == ISD::ZERO_EXTEND) && in CombineExtLoad()
11973 if (N0->getOpcode() != ISD::LOAD) in CombineExtLoad()
11985 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI)) in CombineExtLoad()
11989 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in CombineExtLoad()
12040 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode()); in CombineExtLoad()
12048 assert(N->getOpcode() == ISD::ZERO_EXTEND); in CombineZExtLogicopShiftLoad()
12056 if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in CombineZExtLogicopShiftLoad()
12057 N0.getOpcode() == ISD::XOR) || in CombineZExtLogicopShiftLoad()
12058 N0.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
12059 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
12064 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
12065 N1.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
12066 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
12081 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND) in CombineZExtLogicopShiftLoad()
12098 SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad, in CombineZExtLogicopShiftLoad()
12103 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, in CombineZExtLogicopShiftLoad()
12127 unsigned CastOpcode = Cast->getOpcode(); in matchVSelectOpSizesWithSetCC()
12141 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
12142 VSel.getOperand(0).getOpcode() != ISD::SETCC) in matchVSelectOpSizesWithSetCC()
12273 assert((N->getOpcode() == ISD::SIGN_EXTEND || in foldExtendedSignBitTest()
12274 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); in foldExtendedSignBitTest()
12277 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC || in foldExtendedSignBitTest()
12300 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
12309 if (N0.getOpcode() != ISD::SETCC) in foldSextSetcc()
12383 if (User->getOpcode() != ExtOpcode || User->getValueType(0) != VT) in foldSextSetcc()
12450 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitSIGN_EXTEND()
12454 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSIGN_EXTEND()
12457 if (N00.getOpcode() == ISD::TRUNCATE && in visitSIGN_EXTEND()
12464 if (N0.getOpcode() == ISD::TRUNCATE) { in visitSIGN_EXTEND()
12537 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitSIGN_EXTEND()
12538 N0.getOpcode() == ISD::XOR) && in visitSIGN_EXTEND()
12540 N0.getOperand(1).getOpcode() == ISD::Constant && in visitSIGN_EXTEND()
12541 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitSIGN_EXTEND()
12555 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitSIGN_EXTEND()
12595 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSIGN_EXTEND()
12597 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
12604 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && in visitSIGN_EXTEND()
12606 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
12647 if (N->getOpcode() == ISD::TRUNCATE) { in isTruncateOf()
12653 if (N.getOpcode() != ISD::SETCC || in isTruncateOf()
12678 assert((Extend->getOpcode() == ISD::ZERO_EXTEND || in widenCtPop()
12679 Extend->getOpcode() == ISD::ANY_EXTEND) && "Expected extend op"); in widenCtPop()
12682 if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse()) in widenCtPop()
12700 assert(Extend->getOpcode() == ISD::ZERO_EXTEND && "Expected zero extend."); in widenAbs()
12707 if (Abs.getOpcode() != ISD::ABS || !Abs.hasOneUse()) in widenAbs()
12741 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitZERO_EXTEND()
12763 if (N0.getOpcode() == ISD::TRUNCATE) { in visitZERO_EXTEND()
12807 if (N0.getOpcode() == ISD::AND && in visitZERO_EXTEND()
12808 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitZERO_EXTEND()
12809 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
12841 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || in visitZERO_EXTEND()
12842 N0.getOpcode() == ISD::XOR) && in visitZERO_EXTEND()
12844 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
12845 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitZERO_EXTEND()
12853 if (N0.getOpcode() == ISD::AND) { in visitZERO_EXTEND()
12871 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
12908 if (N0.getOpcode() == ISD::SETCC) { in visitZERO_EXTEND()
12956 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
12958 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitZERO_EXTEND()
12961 if (N0.getOpcode() == ISD::SHL) { in visitZERO_EXTEND()
12977 return DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
13011 if (N0.getOpcode() == ISD::ANY_EXTEND || in visitANY_EXTEND()
13012 N0.getOpcode() == ISD::ZERO_EXTEND || in visitANY_EXTEND()
13013 N0.getOpcode() == ISD::SIGN_EXTEND) in visitANY_EXTEND()
13014 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitANY_EXTEND()
13018 if (N0.getOpcode() == ISD::TRUNCATE) { in visitANY_EXTEND()
13031 if (N0.getOpcode() == ISD::TRUNCATE) in visitANY_EXTEND()
13036 if (N0.getOpcode() == ISD::AND && in visitANY_EXTEND()
13037 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitANY_EXTEND()
13038 N0.getOperand(1).getOpcode() == ISD::Constant && in visitANY_EXTEND()
13089 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) && in visitANY_EXTEND()
13105 if (N0.getOpcode() == ISD::SETCC) { in visitANY_EXTEND()
13159 unsigned Opcode = N->getOpcode(); in visitAssertExt()
13165 if (N0.getOpcode() == Opcode && in visitAssertExt()
13169 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
13170 N0.getOperand(0).getOpcode() == Opcode) { in visitAssertExt()
13189 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
13190 N0.getOperand(0).getOpcode() == ISD::AssertSext && in visitAssertExt()
13220 switch (N0.getOpcode()) { in visitAssertAlign()
13235 return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS); in visitAssertAlign()
13248 unsigned Opc = N->getOpcode(); in reduceLoadWidth()
13326 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
13374 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && in reduceLoadWidth()
13396 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in reduceLoadWidth()
13504 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitSIGN_EXTEND_INREG()
13513 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { in visitSIGN_EXTEND_INREG()
13525 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
13526 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
13527 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { in visitSIGN_EXTEND_INREG()
13532 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in visitSIGN_EXTEND_INREG()
13544 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in visitSIGN_EXTEND_INREG()
13568 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
13653 if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) { in visitSIGN_EXTEND_INREG()
13663 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && in visitSIGN_EXTEND_INREG()
13664 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { in visitSIGN_EXTEND_INREG()
13686 unsigned InregOpcode = N->getOpcode(); in foldExtendVectorInregToExtendOfSubvector()
13702 if (!Src.hasOneUse() || Src.getOpcode() != ISD::CONCAT_VECTORS) in foldExtendVectorInregToExtendOfSubvector()
13724 return N->getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG in visitEXTEND_VECTOR_INREG()
13753 if (N0.getOpcode() == ISD::TRUNCATE) in visitTRUNCATE()
13764 if (N0.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
13765 N0.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
13766 N0.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
13769 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitTRUNCATE()
13780 if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitTRUNCATE()
13792 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND)) in visitTRUNCATE()
13805 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
13831 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) { in visitTRUNCATE()
13843 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in visitTRUNCATE()
13866 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations && in visitTRUNCATE()
13885 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitTRUNCATE()
13886 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in visitTRUNCATE()
13912 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
13933 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
13978 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) { in visitTRUNCATE()
14000 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
14002 if (N00.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
14003 N00.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
14004 N00.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
14019 switch (N0.getOpcode()) { in visitTRUNCATE()
14032 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) { in visitTRUNCATE()
14036 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR); in visitTRUNCATE()
14046 if (((!LegalOperations && N0.getOpcode() == ISD::ADDCARRY) || in visitTRUNCATE()
14047 TLI.isOperationLegal(N0.getOpcode(), VT)) && in visitTRUNCATE()
14053 return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2)); in visitTRUNCATE()
14061 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitTRUNCATE()
14064 hasOperation(N0.getOpcode(), VT)) { in visitTRUNCATE()
14076 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
14084 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
14136 switch (N0.getOpcode()) { in foldBitcastedFPLogic()
14160 LogicOp0.getOpcode() == ISD::BITCAST && in foldBitcastedFPLogic()
14164 if (N0.getOpcode() == ISD::OR) in foldBitcastedFPLogic()
14189 N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() && in visitBITCAST()
14211 if (N0.getOpcode() == ISD::BITCAST) in visitBITCAST()
14255 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
14256 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
14268 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
14272 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
14287 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
14290 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
14306 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && in visitBITCAST()
14370 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
14379 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
14387 if (Op.getOpcode() == ISD::BITCAST && in visitBITCAST()
14442 bool AllowMultipleMaybePoisonOperands = N0.getOpcode() == ISD::BUILD_VECTOR; in visitFREEZE()
14464 if (MaybePoisonOperand.getOpcode() == ISD::UNDEF) in visitFREEZE()
14470 if (FrozenMaybePoisonOperand.getOpcode() == ISD::FREEZE && in visitFREEZE()
14488 if (Op.getOpcode() == ISD::UNDEF) in visitFREEZE()
14492 SDValue R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops); in visitFREEZE()
14578 assert(N.getOpcode() == ISD::FMUL); in isContractableFMUL()
14626 unsigned Opcode = N.getOpcode(); in visitFADDForFMACombine()
14633 if (N.getOpcode() != ISD::FMUL) in visitFADDForFMACombine()
14678 if (FMul.getOpcode() == ISD::FMUL && FMul.hasOneUse()) { in visitFADDForFMACombine()
14685 return FMA.getOpcode() == ISD::DELETED_NODE ? SDValue() : FMA; in visitFADDForFMACombine()
14695 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14709 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14735 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14761 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14779 if (N12.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14796 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14853 if (N.getOpcode() != ISD::FMUL) in visitFSUBForFMACombine()
14898 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
14911 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14926 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14945 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14947 if (N00.getOpcode() == ISD::FNEG) { in visitFSUBForFMACombine()
14968 if (N0.getOpcode() == ISD::FNEG) { in visitFSUBForFMACombine()
14970 if (N00.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14995 unsigned Opcode = N.getOpcode(); in visitFSUBForFMACombine()
15033 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
15055 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
15077 if (isFusedOp(N1) && N1.getOperand(2).getOpcode() == ISD::FP_EXTEND && in visitFSUBForFMACombine()
15101 if (N1.getOpcode() == ISD::FP_EXTEND && isFusedOp(N1.getOperand(0))) { in visitFSUBForFMACombine()
15136 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMADistributiveCombine()
15142 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; in visitFMULForFMADistributiveCombine()
15168 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
15191 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
15233 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFADD()
15271 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) in visitFADD()
15297 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) in visitFADD()
15301 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) in visitFADD()
15312 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
15322 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
15336 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && in visitFADD()
15345 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
15359 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && in visitFADD()
15368 if (N0.getOpcode() == ISD::FADD) { in visitFADD()
15379 if (N1.getOpcode() == ISD::FADD) { in visitFADD()
15391 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD()
15447 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFSUB()
15497 N1.getOpcode() == ISD::FADD) { in visitFSUB()
15530 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFMUL()
15553 N0.getOpcode() == ISD::FMUL) { in visitFMUL()
15567 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() && in visitFMUL()
15606 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && in visitFMUL()
15609 if (Select.getOpcode() != ISD::SELECT) in visitFMUL()
15617 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X && in visitFMUL()
15716 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) && in visitFMA()
15724 if (N0.getOpcode() == ISD::FMUL && in visitFMA()
15746 if (N0.getOpcode() == ISD::FNEG && in visitFMA()
15764 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { in visitFMA()
15820 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) { in combineRepeatedFPDivisors()
15822 if (U->getOperand(1).getOpcode() == ISD::FSQRT && in combineRepeatedFPDivisors()
15869 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFDIV()
15909 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
15912 } else if (N1.getOpcode() == ISD::FP_EXTEND && in visitFDIV()
15913 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
15920 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
15921 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
15928 } else if (N1.getOpcode() == ISD::FMUL) { in visitFDIV()
15932 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
15935 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
15945 if (Y.getOpcode() == ISD::FABS && Y.hasOneUse()) in visitFDIV()
15982 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0)) in visitFDIV()
16011 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFREM()
16050 if ((N1.getOpcode() == ISD::FP_EXTEND || in CanCombineFCOPYSIGN_EXTEND_ROUND()
16051 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
16098 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
16099 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
16103 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
16107 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
16211 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && in foldFPToIntToFP()
16215 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT && in foldFPToIntToFP()
16249 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && in visitSINT_TO_FP()
16259 if (N0.getOpcode() == ISD::ZERO_EXTEND && in visitSINT_TO_FP()
16260 N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() && in visitSINT_TO_FP()
16300 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && in visitUINT_TO_FP()
16318 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
16323 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; in FoldIntToFPToInt()
16324 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT; in FoldIntToFPToInt()
16396 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) in visitFP_ROUND()
16400 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
16428 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse()) { in visitFP_ROUND()
16452 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
16460 if (N0.getOpcode() == ISD::FP16_TO_FP && in visitFP_EXTEND()
16466 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
16521 switch (N0.getOpcode()) { in visitFTRUNC()
16562 if (N0.getOpcode() == ISD::FSUB && in visitFNEG()
16580 unsigned Opc = N->getOpcode(); in visitFMinMax()
16592 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); in visitFMinMax()
16635 if (N0.getOpcode() == ISD::FABS) in visitFABS()
16640 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) in visitFABS()
16656 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) { in visitBRCOND()
16669 if (N1.getOpcode() == ISD::SETCC && in visitBRCOND()
16690 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
16691 (N.getOpcode() == ISD::TRUNCATE && in rebuildSetCC()
16693 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
16695 if (N.getOpcode() == ISD::TRUNCATE) in rebuildSetCC()
16718 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) { in rebuildSetCC()
16721 if (AndOp1.getOpcode() == ISD::Constant) { in rebuildSetCC()
16737 if (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
16744 while (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
16757 if (N.getOpcode() != ISD::XOR) in rebuildSetCC()
16763 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { in rebuildSetCC()
16766 if (isBitwiseNot(N) && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR && in rebuildSetCC()
16805 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) in visitBR_CC()
16875 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || in CombineToPreIndexedLoadStore()
16948 if (Use.getUser()->getOpcode() != ISD::ADD && in CombineToPreIndexedLoadStore()
16949 Use.getUser()->getOpcode() != ISD::SUB) { in CombineToPreIndexedLoadStore()
17045 int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; in CombineToPreIndexedLoadStore()
17046 int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; in CombineToPreIndexedLoadStore()
17084 (PtrUse->getOpcode() != ISD::ADD && PtrUse->getOpcode() != ISD::SUB)) in shouldCombineToPostInc()
17118 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB) { in shouldCombineToPostInc()
17225 assert((Inc.getOpcode() != ISD::TargetConstant || in SplitIndexingFromLoad()
17228 if (Inc.getOpcode() == ISD::TargetConstant) { in SplitIndexingFromLoad()
17820 if (Use->getOpcode() != ISD::BITCAST) in canMergeExpensiveCrossRegisterBankCopy()
18038 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
18046 if (User->getOpcode() != ISD::TRUNCATE) in SliceUpLoad()
18089 if (SliceInst.getOpcode() != ISD::LOAD) in SliceUpLoad()
18091 assert(SliceInst->getOpcode() == ISD::LOAD && in SliceUpLoad()
18111 if (V->getOpcode() != ISD::AND || in CheckForMaskedLoad()
18160 else if (Chain->getOpcode() == ISD::TokenFactor && in CheckForMaskedLoad()
18264 unsigned Opc = Value.getOpcode(); in ReduceLoadOpStoreWidth()
18294 if (Value.getOperand(1).getOpcode() != ISD::Constant) in ReduceLoadOpStoreWidth()
18465 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use. in isMulAddWithConstProfitable()
18501 if (OtherOp->getOpcode() == ISD::ADD && in isMulAddWithConstProfitable()
18618 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
18619 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
18625 Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in mergeStoresOfConstantsOrVecElts()
18795 if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in getStoreMergeCandidates()
18796 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
18892 if (N->getOpcode() == ISD::TokenFactor) { in checkMergeStoreCandidatesForDependencies()
19576 if (Value.getOpcode() == ISD::TargetConstantFP) in replaceStoreOfFPConstant()
19660 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && in visitSTORE()
19724 if ((Value.getOpcode() == ISD::ZERO_EXTEND || in visitSTORE()
19725 Value.getOpcode() == ISD::SIGN_EXTEND || in visitSTORE()
19726 Value.getOpcode() == ISD::ANY_EXTEND) && in visitSTORE()
19744 if (N->getOpcode() != ISD::DELETED_NODE) in visitSTORE()
19824 if ((Value.getOpcode() == ISD::FP_ROUND || in visitSTORE()
19825 Value.getOpcode() == ISD::TRUNCATE) && in visitSTORE()
19845 if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N)) in visitSTORE()
19884 switch (Chain.getOpcode()) { in visitLIFETIME_END()
19964 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR) in splitMergedValStore()
19971 if (Op1.getOpcode() != ISD::SHL) { in splitMergedValStore()
19973 if (Op1.getOpcode() != ISD::SHL) in splitMergedValStore()
19989 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || in splitMergedValStore()
19992 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || in splitMergedValStore()
19999 EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
20002 EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
20038 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in mergeEltWithShuffle()
20066 if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { in mergeEltWithShuffle()
20103 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && in mergeInsertEltWithShuffle()
20133 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && in combineInsertEltToShuffle()
20137 if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() || in combineInsertEltToShuffle()
20204 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
20227 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
20240 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
20301 if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
20308 if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
20314 if (CurVec.getOpcode() == ISD::INSERT_VECTOR_ELT && CurVec.hasOneUse()) in visitINSERT_VECTOR_ELT()
20331 if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
20462 if (!IndexC || !TLI.isBinOp(Vec.getOpcode()) || !Vec.hasOneUse() || in scalarizeExtractedBinop()
20486 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
20569 switch (User->getOpcode()) { in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20598 if (User->getOpcode() != ISD::BUILD_VECTOR) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
20667 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
20674 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
20698 if (VecOp.hasOneUse() && VecOp.getOpcode() == ISD::FREEZE) { in visitEXTRACT_VECTOR_ELT()
20704 if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) || in visitEXTRACT_VECTOR_ELT()
20705 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
20708 assert((VecOp.getOpcode() != ISD::BUILD_VECTOR || in visitEXTRACT_VECTOR_ELT()
20712 VecOp.getOpcode() == ISD::BUILD_VECTOR ? IndexC->getZExtValue() : 0; in visitEXTRACT_VECTOR_ELT()
20739 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && in visitEXTRACT_VECTOR_ELT()
20751 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
20778 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
20796 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_VECTOR_ELT()
20821 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
20834 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
20842 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
20860 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
20895 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
20922 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
20934 } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged && in visitEXTRACT_VECTOR_ELT()
21000 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; in reduceBuildVecExtToExtBuildVec()
21001 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; in reduceBuildVecExtToExtBuildVec()
21056 assert((Cast.getOpcode() == ISD::ANY_EXTEND || in reduceBuildVecExtToExtBuildVec()
21057 Cast.getOpcode() == ISD::ZERO_EXTEND || in reduceBuildVecExtToExtBuildVec()
21095 assert(N->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecTruncToBitCast()
21114 if (Op.getOpcode() == ISD::BITCAST) in reduceBuildVecTruncToBitCast()
21126 if (In.getOpcode() != ISD::TRUNCATE) in reduceBuildVecTruncToBitCast()
21131 if (In.getOpcode() != ISD::SRL) { in reduceBuildVecTruncToBitCast()
21311 assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecToShuffleWithZero()
21338 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || in reduceBuildVecToShuffleWithZero()
21339 Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffleWithZero()
21443 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
21618 bool IsLeftShuffle = L.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
21627 bool IsRightShuffle = R.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
21667 unsigned Opc = Op.getOpcode(); in convertBuildVecZextToZext()
21670 Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && in convertBuildVecZextToZext()
21759 if (Op.getOpcode() != ISD::ZERO_EXTEND) in convertBuildVecZextToBuildVecWithZeros()
21865 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
21935 if (ISD::BITCAST == Op.getOpcode() && in combineConcatVectorOfScalars()
21938 else if (ISD::UNDEF == Op.getOpcode()) in combineConcatVectorOfScalars()
21990 if (Op.getOpcode() != ISD::CONCAT_VECTORS) in combineConcatVectorOfConcatVectors()
22042 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
22094 unsigned CastOpcode = N->getOperand(0).getOpcode(); in combineConcatVectorOfCasts()
22119 if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() || in combineConcatVectorOfCasts()
22277 if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse()) { in visitCONCAT_VECTORS()
22288 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
22300 if (Scalar->getOpcode() == ISD::TRUNCATE && in visitCONCAT_VECTORS()
22332 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode(); in visitCONCAT_VECTORS()
22344 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
22356 if (ISD::UNDEF == Op.getOpcode()) in visitCONCAT_VECTORS()
22359 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
22415 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
22447 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
22452 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && in getSubVectorSrc()
22466 unsigned BinOpcode = BinOp.getOpcode(); in narrowInsertExtractVectorBinOp()
22515 unsigned BOpcode = BinOp.getOpcode(); in narrowExtractedVectorBinOp()
22596 if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2) in narrowExtractedVectorBinOp()
22694 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && in foldExtractSubvectorFromShuffleVector()
22848 if (ExtIdx == 0 && V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) { in visitEXTRACT_SUBVECTOR()
22858 if (V.getOpcode() == ISD::SPLAT_VECTOR) in visitEXTRACT_SUBVECTOR()
22865 if (V.getOpcode() == ISD::BITCAST && in visitEXTRACT_SUBVECTOR()
22916 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
22959 if (V.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_SUBVECTOR()
22991 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
23033 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
23034 N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
23198 if (S.getOpcode() == ISD::BUILD_VECTOR) { in combineShuffleOfScalars()
23200 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
23453 unsigned Opcode = N0.getOpcode(); in combineTruncationShuffle()
23612 if (Op0.getOpcode() != ISD::BITCAST) in combineShuffleOfBitcast()
23616 (!Op1.isUndef() && (Op1.getOpcode() != ISD::BITCAST || in combineShuffleOfBitcast()
23756 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceShuffleOfInsert()
23861 TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) { in visitVECTOR_SHUFFLE()
23871 DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags()); in visitVECTOR_SHUFFLE()
23881 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0) in visitVECTOR_SHUFFLE()
23884 if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT) in visitVECTOR_SHUFFLE()
23891 if (N0.getOpcode() == ISD::BITCAST && N0.getOperand(0).hasOneUse() && in visitVECTOR_SHUFFLE()
23893 (N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR || in visitVECTOR_SHUFFLE()
23894 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR)) { in visitVECTOR_SHUFFLE()
23911 if (V->getOpcode() == ISD::BITCAST) { in visitVECTOR_SHUFFLE()
23918 if (V->getOpcode() == ISD::BUILD_VECTOR) { in visitVECTOR_SHUFFLE()
23973 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
23976 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
23985 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() && in visitVECTOR_SHUFFLE()
24014 assert(RHS.getOpcode() == ISD::CONCAT_VECTORS && "Can't find subvectors"); in visitVECTOR_SHUFFLE()
24059 if (N1.getOpcode() == ISD::CONCAT_VECTORS) in visitVECTOR_SHUFFLE()
24062 if (N0.getOpcode() == ISD::CONCAT_VECTORS) { in visitVECTOR_SHUFFLE()
24136 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitVECTOR_SHUFFLE()
24141 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { in visitVECTOR_SHUFFLE()
24315 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
24316 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
24333 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
24334 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
24348 if (N->getOperand(i).getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
24375 unsigned SrcOpcode = N0.getOpcode(); in visitVECTOR_SHUFFLE()
24378 (SrcOpcode == N1.getOpcode() && N->isOnlyUserOf(N1.getNode())))) { in visitVECTOR_SHUFFLE()
24389 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
24390 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
24391 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
24392 Op11.getOpcode() == ISD::VECTOR_SHUFFLE)) { in visitVECTOR_SHUFFLE()
24473 unsigned Opcode = Scalar.getOpcode(); in visitSCALAR_TO_VECTOR()
24488 if (C && EE.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitSCALAR_TO_VECTOR()
24566 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
24572 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR) in visitINSERT_SUBVECTOR()
24579 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && in visitINSERT_SUBVECTOR()
24580 N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
24593 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
24610 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
24619 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
24627 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) && in visitINSERT_SUBVECTOR()
24628 N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
24665 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
24680 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
24701 if (N0->getOpcode() == ISD::FP16_TO_FP) in visitFP_TO_FP16()
24711 if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) { in visitFP16_TO_FP()
24726 if (N0->getOpcode() == ISD::BF16_TO_FP) in visitFP_TO_BF16()
24735 unsigned Opcode = N->getOpcode(); in visitVECREDUCE()
24761 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitVECREDUCE()
24777 if (N->getOpcode() == ISD::VP_GATHER) in visitVPOp()
24781 if (N->getOpcode() == ISD::VP_SCATTER) in visitVPOp()
24789 if (auto EVLIdx = ISD::getVPExplicitVectorLengthIdx(N->getOpcode())) in visitVPOp()
24791 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) in visitVPOp()
24800 if (ISD::isVPBinaryOp(N->getOpcode())) in visitVPOp()
24812 if (ISD::isVPReduction(N->getOpcode())) in visitVPOp()
24823 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!"); in XformToShuffleWithZero()
24835 if (RHS.getOpcode() != ISD::BUILD_VECTOR) in XformToShuffleWithZero()
24913 unsigned Opcode = N->getOpcode(); in scalarizeBinOpOfSplats()
24926 bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR && in scalarizeBinOpOfSplats()
24927 N1.getOpcode() == ISD::SPLAT_VECTOR; in scalarizeBinOpOfSplats()
24942 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() && in scalarizeBinOpOfSplats()
24961 unsigned Opcode = N->getOpcode(); in SimplifyVCastOp()
24972 (N0.getOpcode() == ISD::SPLAT_VECTOR || in SimplifyVCastOp()
24996 unsigned Opcode = N->getOpcode(); in SimplifyVBinOp()
25026 Shuf0->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
25035 Shuf1->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
25048 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() && in SimplifyVBinOp()
25049 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() && in SimplifyVBinOp()
25069 return Concat.getOpcode() == ISD::CONCAT_VECTORS && in SimplifyVBinOp()
25106 assert(N0.getOpcode() == ISD::SETCC && in SimplifySelect()
25118 if (SCC.getOpcode() == ISD::SELECT_CC) { in SimplifySelect()
25146 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
25153 if (TheSelect->getOpcode() == ISD::SELECT_CC) { in SimplifySelectOps()
25160 if (Cmp.getOpcode() == ISD::SETCC) { in SimplifySelectOps()
25180 if (LHS.getOpcode() != RHS.getOpcode() || in SimplifySelectOps()
25188 if (LHS.getOpcode() == ISD::LOAD) { in SimplifySelectOps()
25217 LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
25218 RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
25219 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), in SimplifySelectOps()
25246 if (TheSelect->getOpcode() == ISD::SELECT) { in SimplifySelectOps()
25409 unsigned BinOpc = N1.getOpcode(); in foldSelectOfBinops()
25410 if (!TLI.isBinOp(BinOpc) || (N2.getOpcode() != BinOpc)) in foldSelectOfBinops()
25457 bool IsFabs = N->getOpcode() == ISD::FABS; in foldSignChangeInBitcast()
25460 if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse()) in foldSignChangeInBitcast()
25588 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && in SimplifySelectCC()
25681 if ((Count.getOpcode() == ISD::CTTZ || in SimplifySelectCC()
25682 Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && in SimplifySelectCC()
25688 if ((Count.getOpcode() == ISD::CTLZ || in SimplifySelectCC()
25689 Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) && in SimplifySelectCC()
26180 switch (C.getOpcode()) { in GatherAllAliases()
26243 if (Chain.getOpcode() == ISD::TokenFactor) { in GatherAllAliases()