Lines Matching refs:DstInt
1439 LiveInterval &DstInt = LIS->getInterval(DstReg); in reMaterializeTrivialDef() local
1440 for (LiveInterval::SubRange &SR : DstInt.subranges()) { in reMaterializeTrivialDef()
1467 if (NewIdx == 0 && DstInt.hasSubRanges()) { in reMaterializeTrivialDef()
1473 for (LiveInterval::SubRange &SR : DstInt.subranges()) { in reMaterializeTrivialDef()
1479 LiveInterval::SubRange *SR = DstInt.createSubRange(Alloc, MaxMask); in reMaterializeTrivialDef()
1492 if (NewIdx != 0 && DstInt.hasSubRanges()) { in reMaterializeTrivialDef()
1500 for (LiveInterval::SubRange &SR : DstInt.subranges()) { in reMaterializeTrivialDef()
1521 DstInt.removeEmptySubRanges(); in reMaterializeTrivialDef()
1753 LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg); in updateRegDefsUses() local
1755 if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) { in updateRegDefsUses()
1764 addUndefFlag(*DstInt, UseIdx, MO, SubReg); in updateRegDefsUses()
1788 if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr()) in updateRegDefsUses()
1789 Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI)); in updateRegDefsUses()
1806 if (!DstInt->hasSubRanges()) { in updateRegDefsUses()
1808 LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg(DstInt->reg()); in updateRegDefsUses()
1811 DstInt->createSubRangeFrom(Allocator, UsedLanes, *DstInt); in updateRegDefsUses()
1816 DstInt->createSubRange(Allocator, UnusedLanes); in updateRegDefsUses()
1822 addUndefFlag(*DstInt, UseIdx, MO, SubUseIdx); in updateRegDefsUses()