Lines Matching defs:cpu_reg
360 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *,
2845 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg,
2852 val = REG_RD_IND(sc, cpu_reg->mode);
2853 val |= cpu_reg->mode_value_halt;
2854 REG_WR_IND(sc, cpu_reg->mode, val);
2855 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2858 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2867 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2876 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2885 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2894 offset = cpu_reg->spad_base +
2895 (fw->rodata_addr - cpu_reg->mips_view_base);
2904 REG_WR_IND(sc, cpu_reg->inst, 0);
2905 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2908 val = REG_RD_IND(sc, cpu_reg->mode);
2909 val &= ~cpu_reg->mode_value_halt;
2910 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2911 REG_WR_IND(sc, cpu_reg->mode, val);
2925 struct cpu_reg cpu_reg;
2944 cpu_reg.mode = BNX_RXP_CPU_MODE;
2945 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT;
2946 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA;
2947 cpu_reg.state = BNX_RXP_CPU_STATE;
2948 cpu_reg.state_value_clear = 0xffffff;
2949 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE;
2950 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK;
2951 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER;
2952 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION;
2953 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT;
2954 cpu_reg.spad_base = BNX_RXP_SCRATCH;
2955 cpu_reg.mips_view_base = 0x8000000;
2988 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
2991 cpu_reg.mode = BNX_TXP_CPU_MODE;
2992 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT;
2993 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA;
2994 cpu_reg.state = BNX_TXP_CPU_STATE;
2995 cpu_reg.state_value_clear = 0xffffff;
2996 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE;
2997 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK;
2998 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER;
2999 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION;
3000 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT;
3001 cpu_reg.spad_base = BNX_TXP_SCRATCH;
3002 cpu_reg.mips_view_base = 0x8000000;
3035 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
3038 cpu_reg.mode = BNX_TPAT_CPU_MODE;
3039 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT;
3040 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA;
3041 cpu_reg.state = BNX_TPAT_CPU_STATE;
3042 cpu_reg.state_value_clear = 0xffffff;
3043 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE;
3044 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK;
3045 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER;
3046 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION;
3047 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT;
3048 cpu_reg.spad_base = BNX_TPAT_SCRATCH;
3049 cpu_reg.mips_view_base = 0x8000000;
3082 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
3085 cpu_reg.mode = BNX_COM_CPU_MODE;
3086 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT;
3087 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA;
3088 cpu_reg.state = BNX_COM_CPU_STATE;
3089 cpu_reg.state_value_clear = 0xffffff;
3090 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE;
3091 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK;
3092 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER;
3093 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION;
3094 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT;
3095 cpu_reg.spad_base = BNX_COM_SCRATCH;
3096 cpu_reg.mips_view_base = 0x8000000;
3128 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
3138 cpu_reg.mode = BNX_RXP_CPU_MODE;
3139 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT;
3140 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA;
3141 cpu_reg.state = BNX_RXP_CPU_STATE;
3142 cpu_reg.state_value_clear = 0xffffff;
3143 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE;
3144 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK;
3145 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER;
3146 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION;
3147 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT;
3148 cpu_reg.spad_base = BNX_RXP_SCRATCH;
3149 cpu_reg.mips_view_base = 0x8000000;
3182 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
3185 cpu_reg.mode = BNX_TXP_CPU_MODE;
3186 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT;
3187 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA;
3188 cpu_reg.state = BNX_TXP_CPU_STATE;
3189 cpu_reg.state_value_clear = 0xffffff;
3190 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE;
3191 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK;
3192 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER;
3193 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION;
3194 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT;
3195 cpu_reg.spad_base = BNX_TXP_SCRATCH;
3196 cpu_reg.mips_view_base = 0x8000000;
3229 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
3232 cpu_reg.mode = BNX_TPAT_CPU_MODE;
3233 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT;
3234 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA;
3235 cpu_reg.state = BNX_TPAT_CPU_STATE;
3236 cpu_reg.state_value_clear = 0xffffff;
3237 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE;
3238 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK;
3239 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER;
3240 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION;
3241 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT;
3242 cpu_reg.spad_base = BNX_TPAT_SCRATCH;
3243 cpu_reg.mips_view_base = 0x8000000;
3276 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
3279 cpu_reg.mode = BNX_COM_CPU_MODE;
3280 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT;
3281 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA;
3282 cpu_reg.state = BNX_COM_CPU_STATE;
3283 cpu_reg.state_value_clear = 0xffffff;
3284 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE;
3285 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK;
3286 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER;
3287 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION;
3288 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT;
3289 cpu_reg.spad_base = BNX_COM_SCRATCH;
3290 cpu_reg.mips_view_base = 0x8000000;
3322 bnx_load_cpu_fw(sc, &cpu_reg, &fw);