Lines Matching defs:spdmem_ddr3
420 struct spdmem_ddr3 { /* Dual Data Rate 3 SDRAM */ struct
426 uint8_t ddr3_romrev;
427 uint8_t ddr3_type;
428 uint8_t ddr3_mod_type;
464 uint8_t ddr3_mtb_dividend; /* 0x0108 = 0.1250ns */
465 uint8_t ddr3_mtb_divisor; /* 0x010f = 0.0625ns */
466 uint8_t ddr3_tCKmin_mtb;
467 uint8_t ddr3_unused3;
468 uint16_t ddr3_CAS_sup; /* Bit 0 ==> CAS 4 cycles */
469 uint8_t ddr3_tAAmin_mtb;
470 uint8_t ddr3_tWRmin;
471 uint8_t ddr3_tRCDmin_mtb;
472 uint8_t ddr3_tRRDmin;
473 uint8_t ddr3_tRPmin_mtb;
478 uint8_t ddr3_tRAS_lsb;
479 uint8_t ddr3_tRCmin_mtb_lsb;
480 uint8_t ddr3_tRFCmin_lsb;
481 uint8_t ddr3_tRFCmin_msb;
482 uint8_t ddr3_tWTRmin;
483 uint8_t ddr3_tRTPmin;
487 uint8_t ddr3_tFAW_lsb;
488 uint8_t ddr3_output_drvrs;
505 uint8_t ddr3_tCKmin_ftb;
506 uint8_t ddr3_tAAmin_ftb;
507 uint8_t ddr3_tRCDmin_ftb;
508 uint8_t ddr3_tRPmin_ftb;
509 uint8_t ddr3_tRCmin_ftb;
510 uint8_t ddr3_unused4[2];
511 uint8_t ddr3_MAC;
512 uint8_t ddr3_unused4a[18];
513 uint8_t ddr3_mod_height;
514 uint8_t ddr3_mod_thickness;
515 uint8_t ddr3_ref_card;
516 uint8_t ddr3_mapping;
517 uint8_t ddr3_unused5[53];
518 uint8_t ddr3_mfgID_lsb;
519 uint8_t ddr3_mfgID_msb;
520 uint8_t ddr3_mfgloc;
521 uint8_t ddr3_mfg_year;
522 uint8_t ddr3_mfg_week;
523 uint8_t ddr3_serial[4];
524 uint16_t ddr3_crc;
525 uint8_t ddr3_part[18];
526 uint8_t ddr3_rev[2];
527 uint8_t ddr3_dram_mfgID_lsb;
528 uint8_t ddr3_dram_mfgID_msb;
529 uint8_t ddr3_vendor[26];