Lines Matching defs:sc
79 #define GENET_LOCK(sc) mutex_enter(&(sc)->sc_lock)
80 #define GENET_UNLOCK(sc) mutex_exit(&(sc)->sc_lock)
81 #define GENET_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_lock))
83 #define GENET_TXLOCK(sc) mutex_enter(&(sc)->sc_txlock)
84 #define GENET_TXUNLOCK(sc) mutex_exit(&(sc)->sc_txlock)
85 #define GENET_ASSERT_TXLOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_txlock))
87 #define RD4(sc, reg) \
88 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
89 #define WR4(sc, reg, val) \
90 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
95 struct genet_softc *sc = device_private(dev);
98 WR4(sc, GENET_MDIO_CMD,
103 if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0) {
104 *val = RD4(sc, GENET_MDIO_CMD) & 0xffff;
122 struct genet_softc *sc = device_private(dev);
125 WR4(sc, GENET_MDIO_CMD,
130 if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0)
145 genet_update_link(struct genet_softc *sc)
147 struct mii_data *mii = &sc->sc_mii;
159 val = RD4(sc, GENET_EXT_RGMII_OOB_CTRL);
163 if (sc->sc_phy_mode == GENET_PHY_MODE_RGMII)
167 WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val);
169 val = RD4(sc, GENET_UMAC_CMD);
172 WR4(sc, GENET_UMAC_CMD, val);
178 struct genet_softc * const sc = ifp->if_softc;
180 genet_update_link(sc);
184 genet_setup_txdesc(struct genet_softc *sc, int index, int flags,
191 WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
192 WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
193 WR4(sc, GENET_TX_DESC_STATUS(index), status);
197 genet_setup_txbuf(struct genet_softc *sc, int index, struct mbuf *m)
205 if (sc->sc_tx.queued >= TX_DESC_COUNT - 1)
208 error = bus_dmamap_load_mbuf(sc->sc_tx.buf_tag,
209 sc->sc_tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
211 device_printf(sc->sc_dev,
216 device_printf(sc->sc_dev,
221 segs = sc->sc_tx.buf_map[index].map->dm_segs;
222 nsegs = sc->sc_tx.buf_map[index].map->dm_nsegs;
224 nospace = sc->sc_tx.queued >= TX_DESC_COUNT - nsegs;
226 bus_dmamap_unload(sc->sc_tx.buf_tag,
227 sc->sc_tx.buf_map[index].map);
232 bus_dmamap_sync(sc->sc_tx.buf_tag, sc->sc_tx.buf_map[index].map,
233 0, sc->sc_tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE);
236 sc->sc_tx.buf_map[index].mbuf = m;
246 genet_setup_txdesc(sc, cur, flags, segs[i].ds_addr,
258 genet_setup_rxdesc(struct genet_softc *sc, int index,
261 WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
262 WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
266 genet_setup_rxbuf(struct genet_softc *sc, int index, struct mbuf *m)
270 error = bus_dmamap_load_mbuf(sc->sc_rx.buf_tag,
271 sc->sc_rx.buf_map[index].map, m, BUS_DMA_READ | BUS_DMA_NOWAIT);
275 bus_dmamap_sync(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map,
276 0, sc->sc_rx.buf_map[index].map->dm_mapsize,
279 sc->sc_rx.buf_map[index].mbuf = m;
280 genet_setup_rxdesc(sc, index,
281 sc->sc_rx.buf_map[index].map->dm_segs[0].ds_addr,
282 sc->sc_rx.buf_map[index].map->dm_segs[0].ds_len);
288 genet_alloc_mbufcl(struct genet_softc *sc)
300 genet_enable_intr(struct genet_softc *sc)
302 WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK,
307 genet_disable_intr(struct genet_softc *sc)
310 WR4(sc, GENET_INTRL2_CPU_SET_MASK, 0xffffffff);
311 WR4(sc, GENET_INTRL2_CPU_CLEAR, 0xffffffff);
317 struct genet_softc *sc = softc;
318 struct mii_data *mii = &sc->sc_mii;
320 GENET_LOCK(sc);
322 if ((sc->sc_if_flags & IFF_RUNNING) != 0)
323 callout_schedule(&sc->sc_stat_ch, hz);
324 GENET_UNLOCK(sc);
328 genet_setup_rxfilter_mdf(struct genet_softc *sc, u_int n, const uint8_t *ea)
333 WR4(sc, GENET_UMAC_MDF_ADDR0(n), addr0);
334 WR4(sc, GENET_UMAC_MDF_ADDR1(n), addr1);
338 genet_setup_rxfilter(struct genet_softc *sc)
340 struct ethercom *ec = &sc->sc_ec;
347 GENET_ASSERT_LOCKED(sc);
351 cmd = RD4(sc, GENET_UMAC_CMD);
367 if ((sc->sc_if_flags & IFF_PROMISC) != 0) {
373 genet_setup_rxfilter_mdf(sc, 0, ifp->if_broadcastaddr);
374 genet_setup_rxfilter_mdf(sc, 1, CLLADDR(ifp->if_sadl));
377 genet_setup_rxfilter_mdf(sc, n, enm->enm_addrlo);
384 WR4(sc, GENET_UMAC_CMD, cmd);
385 WR4(sc, GENET_UMAC_MDF_CTRL, mdf_ctrl);
391 genet_reset(struct genet_softc *sc)
395 val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);
397 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
401 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
404 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0);
407 WR4(sc, GENET_UMAC_CMD, 0);
408 WR4(sc, GENET_UMAC_CMD,
411 WR4(sc, GENET_UMAC_CMD, 0);
413 WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT |
415 WR4(sc, GENET_UMAC_MIB_CTRL, 0);
417 WR4(sc, GENET_UMAC_MAX_FRAME_LEN, 1536);
419 val = RD4(sc, GENET_RBUF_CTRL);
421 WR4(sc, GENET_RBUF_CTRL, val);
423 WR4(sc, GENET_RBUF_TBUF_SIZE_CTRL, 1);
429 genet_set_rxthresh(struct genet_softc *sc, int qid, int usecs, int count)
446 WR4(sc, GENET_RX_DMA_MBUF_DONE_THRES(qid), count);
448 val = RD4(sc, GENET_RX_DMA_RING_TIMEOUT(qid));
451 WR4(sc, GENET_RX_DMA_RING_TIMEOUT(qid), val);
455 genet_set_txthresh(struct genet_softc *sc, int qid, int count)
462 WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), count);
466 genet_init_rings(struct genet_softc *sc, int qid)
472 sc->sc_tx.queued = 0;
473 sc->sc_tx.cidx = sc->sc_tx.pidx = 0;
475 WR4(sc, GENET_TX_SCB_BURST_SIZE, 0x08);
477 WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0);
478 WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0);
479 WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), 0);
480 WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), 0);
481 WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid),
484 WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0);
485 WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0);
486 WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),
488 WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);
489 WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);
490 WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);
491 WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);
494 genet_set_txthresh(sc, qid, 10);
496 WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */
499 val = RD4(sc, GENET_TX_DMA_CTRL);
502 WR4(sc, GENET_TX_DMA_CTRL, val);
506 sc->sc_rx.cidx = sc->sc_rx.pidx = 0;
508 WR4(sc, GENET_RX_SCB_BURST_SIZE, 0x08);
510 WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0);
511 WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0);
512 WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), 0);
513 WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), 0);
514 WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid),
517 WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0);
518 WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0);
519 WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid),
521 WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0);
522 WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid),
525 WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);
526 WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);
532 genet_set_rxthresh(sc, qid, 57, 10);
534 WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */
537 val = RD4(sc, GENET_RX_DMA_CTRL);
540 WR4(sc, GENET_RX_DMA_CTRL, val);
544 genet_init_locked(struct genet_softc *sc)
546 struct ifnet *ifp = &sc->sc_ec.ec_if;
547 struct mii_data *mii = &sc->sc_mii;
551 GENET_ASSERT_LOCKED(sc);
552 GENET_ASSERT_TXLOCKED(sc);
557 if (sc->sc_phy_mode == GENET_PHY_MODE_RGMII ||
558 sc->sc_phy_mode == GENET_PHY_MODE_RGMII_ID ||
559 sc->sc_phy_mode == GENET_PHY_MODE_RGMII_RXID ||
560 sc->sc_phy_mode == GENET_PHY_MODE_RGMII_TXID)
561 WR4(sc, GENET_SYS_PORT_CTRL,
564 WR4(sc, GENET_SYS_PORT_CTRL, 0);
569 WR4(sc, GENET_UMAC_MAC0, val);
571 WR4(sc, GENET_UMAC_MAC1, val);
574 sc->sc_if_flags = ifp->if_flags;
575 genet_setup_rxfilter(sc);
578 genet_init_rings(sc, GENET_DMA_DEFAULT_QUEUE);
581 val = RD4(sc, GENET_UMAC_CMD);
584 WR4(sc, GENET_UMAC_CMD, val);
587 genet_enable_intr(sc);
589 GENET_ASSERT_TXLOCKED(sc);
590 sc->sc_txrunning = true;
593 sc->sc_if_flags |= IFF_RUNNING;
596 callout_schedule(&sc->sc_stat_ch, hz);
604 struct genet_softc *sc = ifp->if_softc;
607 GENET_LOCK(sc);
608 GENET_TXLOCK(sc);
609 error = genet_init_locked(sc);
610 GENET_TXUNLOCK(sc);
611 GENET_UNLOCK(sc);
617 genet_free_txbuf(struct genet_softc *sc, int index)
621 bmap = &sc->sc_tx.buf_map[index];
626 bus_dmamap_sync(sc->sc_tx.buf_tag, bmap->map,
630 bus_dmamap_unload(sc->sc_tx.buf_tag, bmap->map);
638 genet_stop_locked(struct genet_softc *sc, int disable)
640 struct ifnet *ifp = &sc->sc_ec.ec_if;
644 GENET_ASSERT_LOCKED(sc);
646 GENET_TXLOCK(sc);
647 sc->sc_txrunning = false;
648 GENET_TXUNLOCK(sc);
650 callout_halt(&sc->sc_stat_ch, &sc->sc_lock);
652 mii_down(&sc->sc_mii);
655 val = RD4(sc, GENET_UMAC_CMD);
657 WR4(sc, GENET_UMAC_CMD, val);
660 val = RD4(sc, GENET_RX_DMA_CTRL);
662 WR4(sc, GENET_RX_DMA_CTRL, val);
665 val = RD4(sc, GENET_TX_DMA_CTRL);
667 WR4(sc, GENET_TX_DMA_CTRL, val);
670 WR4(sc, GENET_UMAC_TX_FLUSH, 1);
672 WR4(sc, GENET_UMAC_TX_FLUSH, 0);
675 val = RD4(sc, GENET_UMAC_CMD);
677 WR4(sc, GENET_UMAC_CMD, val);
680 genet_disable_intr(sc);
684 genet_free_txbuf(sc, i);
686 sc->sc_if_flags &= ~IFF_RUNNING;
693 struct genet_softc * const sc = ifp->if_softc;
695 GENET_LOCK(sc);
696 genet_stop_locked(sc, disable);
697 GENET_UNLOCK(sc);
701 genet_rxintr(struct genet_softc *sc, int qid)
703 struct ifnet *ifp = &sc->sc_ec.ec_if;
709 pidx = RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)) & 0xffff;
710 total = (pidx - sc->sc_rx.cidx) & 0xffff;
714 index = sc->sc_rx.cidx % RX_DESC_COUNT;
716 status = RD4(sc, GENET_RX_DESC_STATUS(index));
720 device_printf(sc->sc_dev, "overrun\n");
722 device_printf(sc->sc_dev, "CRC error\n");
724 device_printf(sc->sc_dev, "receive error\n");
726 device_printf(sc->sc_dev, "frame error\n");
728 device_printf(sc->sc_dev, "length error\n");
734 device_printf(sc->sc_dev, "OWN %d of %d\n",n,total);
742 m = sc->sc_rx.buf_map[index].mbuf;
744 if ((m0 = genet_alloc_mbufcl(sc)) == NULL) {
748 MCLAIM(m0, &sc->sc_ec.ec_rx_mowner);
751 if (sc->sc_rx.buf_map[index].map->dm_mapsize > 0) {
752 bus_dmamap_sync(sc->sc_rx.buf_tag,
753 sc->sc_rx.buf_map[index].map,
754 0, sc->sc_rx.buf_map[index].map->dm_mapsize,
757 bus_dmamap_unload(sc->sc_rx.buf_tag, sc->sc_rx.buf_map[index].map);
758 sc->sc_rx.buf_map[index].mbuf = NULL;
760 error = genet_setup_rxbuf(sc, index, m0);
767 device_printf(sc->sc_dev,
785 sc->sc_rx.cidx = (sc->sc_rx.cidx + 1) & 0xffff;
786 WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), sc->sc_rx.cidx);
790 rnd_add_uint32(&sc->sc_rndsource, pkts);
794 genet_txintr(struct genet_softc *sc, int qid)
796 struct ifnet *ifp = &sc->sc_ec.ec_if;
799 cidx = RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)) & 0xffff;
800 i = sc->sc_tx.cidx % TX_DESC_COUNT;
801 while (sc->sc_tx.cidx != cidx) {
802 pkts += genet_free_txbuf(sc, i);
804 sc->sc_tx.cidx = (sc->sc_tx.cidx + 1) & 0xffff;
809 rnd_add_uint32(&sc->sc_rndsource, pkts);
816 genet_start_locked(struct genet_softc *sc)
818 struct ifnet *ifp = &sc->sc_ec.ec_if;
822 GENET_ASSERT_TXLOCKED(sc);
824 if (!sc->sc_txrunning)
829 index = sc->sc_tx.pidx % TX_DESC_COUNT;
832 sc->sc_tx.queued = (RD4(sc, GENET_TX_DMA_PROD_INDEX(qid))
833 - sc->sc_tx.cidx) & 0xffff;
836 if (sc->sc_tx.queued >= TX_DESC_COUNT - 1)
844 nsegs = genet_setup_txbuf(sc, index, m);
858 sc->sc_tx.queued += nsegs;
859 sc->sc_tx.pidx = (sc->sc_tx.pidx + nsegs) & 0xffff;
864 WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), sc->sc_tx.pidx);
870 struct genet_softc *sc = ifp->if_softc;
872 GENET_TXLOCK(sc);
873 genet_start_locked(sc);
874 GENET_TXUNLOCK(sc);
880 struct genet_softc *sc = arg;
883 val = RD4(sc, GENET_INTRL2_CPU_STAT);
884 val &= ~RD4(sc, GENET_INTRL2_CPU_STAT_MASK);
885 WR4(sc, GENET_INTRL2_CPU_CLEAR, val);
888 GENET_LOCK(sc);
889 genet_rxintr(sc, GENET_DMA_DEFAULT_QUEUE);
890 GENET_UNLOCK(sc);
894 genet_txintr(sc, GENET_DMA_DEFAULT_QUEUE);
903 struct genet_softc *sc = ifp->if_softc;
926 GENET_LOCK(sc);
927 if ((sc->sc_if_flags & IFF_RUNNING) != 0)
928 genet_setup_rxfilter(sc);
929 GENET_UNLOCK(sc);
938 struct genet_softc * const sc = ifp->if_softc;
942 GENET_LOCK(sc);
944 u_short change = ifp->if_flags ^ sc->sc_if_flags;
945 sc->sc_if_flags = ifp->if_flags;
950 if ((sc->sc_if_flags & IFF_RUNNING) != 0)
951 genet_setup_rxfilter(sc);
953 GENET_UNLOCK(sc);
959 genet_get_eaddr(struct genet_softc *sc, uint8_t *eaddr)
961 prop_dictionary_t prop = device_properties(sc->sc_dev);
976 val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);
978 maclo = RD4(sc, GENET_UMAC_MAC0);
979 machi = RD4(sc, GENET_UMAC_MAC1) & 0xffff;
997 genet_setup_dma(struct genet_softc *sc, int qid)
1003 sc->sc_tx.buf_tag = sc->sc_dmat;
1005 error = bus_dmamap_create(sc->sc_tx.buf_tag, MCLBYTES,
1007 &sc->sc_tx.buf_map[i].map);
1009 device_printf(sc->sc_dev,
1016 sc->sc_rx.buf_tag = sc->sc_dmat;
1018 error = bus_dmamap_create(sc->sc_rx.buf_tag, MCLBYTES,
1020 &sc->sc_rx.buf_map[i].map);
1022 device_printf(sc->sc_dev,
1026 if ((m = genet_alloc_mbufcl(sc)) == NULL) {
1027 device_printf(sc->sc_dev, "cannot allocate RX mbuf\n");
1030 error = genet_setup_rxbuf(sc, i, m);
1032 device_printf(sc->sc_dev, "cannot create RX buffer\n");
1041 genet_claim_rxring(struct genet_softc *sc, int qid)
1048 m = sc->sc_rx.buf_map[i].mbuf;
1050 MCLAIM(m, &sc->sc_ec.ec_rx_mowner);
1056 genet_attach(struct genet_softc *sc)
1058 struct mii_data *mii = &sc->sc_mii;
1059 struct ifnet *ifp = &sc->sc_ec.ec_if;
1064 const uint32_t rev = RD4(sc, GENET_SYS_REV_CTRL);
1077 switch (sc->sc_phy_mode) {
1095 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET);
1096 mutex_init(&sc->sc_txlock, MUTEX_DEFAULT, IPL_NET);
1097 callout_init(&sc->sc_stat_ch, CALLOUT_MPSAFE);
1098 callout_setfunc(&sc->sc_stat_ch, genet_tick, sc);
1100 genet_get_eaddr(sc, eaddr);
1101 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", ether_sprintf(eaddr));
1104 genet_reset(sc);
1107 if (genet_setup_dma(sc, GENET_DMA_DEFAULT_QUEUE) != 0) {
1108 aprint_error_dev(sc->sc_dev, "failed to setup DMA descriptors\n");
1113 ifp->if_softc = sc;
1114 snprintf(ifp->if_xname, IFNAMSIZ, "%s", device_xname(sc->sc_dev));
1127 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
1130 sc->sc_ec.ec_mii = mii;
1136 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, MII_OFFSET_ANY,
1140 aprint_error_dev(sc->sc_dev, "no PHY found!\n");
1151 ether_set_ifflags_cb(&sc->sc_ec, genet_ifflags_cb);
1155 genet_claim_rxring(sc, GENET_DMA_DEFAULT_QUEUE);
1157 rnd_attach_source(&sc->sc_rndsource, ifp->if_xname, RND_TYPE_NET,
1173 struct genet_softc * const sc = device_private(dev);
1176 printf("TX CIDX = %08x (soft)\n", sc->sc_tx.cidx);
1177 printf("TX CIDX = %08x\n", RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)));
1178 printf("TX PIDX = %08x (soft)\n", sc->sc_tx.pidx);
1179 printf("TX PIDX = %08x\n", RD4(sc, GENET_TX_DMA_PROD_INDEX(qid)));
1181 printf("RX CIDX = %08x (soft)\n", sc->sc_rx.cidx);
1182 printf("RX CIDX = %08x\n", RD4(sc, GENET_RX_DMA_CONS_INDEX(qid)));
1183 printf("RX PIDX = %08x (soft)\n", sc->sc_rx.pidx);
1184 printf("RX PIDX = %08x\n", RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)));