Lines Matching refs:sc
143 athn_attach(struct athn_softc *sc) in athn_attach() argument
145 struct ieee80211com *ic = &sc->sc_ic; in athn_attach()
146 struct ifnet *ifp = &sc->sc_if; in athn_attach()
151 athn_get_chipid(sc); in athn_attach()
153 if ((error = athn_reset_power_on(sc)) != 0) { in athn_attach()
154 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); in athn_attach()
158 if ((error = athn_set_power_awake(sc)) != 0) { in athn_attach()
159 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); in athn_attach()
163 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) in athn_attach()
164 error = ar5416_attach(sc); in athn_attach()
165 else if (AR_SREV_9280(sc)) in athn_attach()
166 error = ar9280_attach(sc); in athn_attach()
167 else if (AR_SREV_9285(sc)) in athn_attach()
168 error = ar9285_attach(sc); in athn_attach()
170 else if (AR_SREV_9271(sc)) in athn_attach()
171 error = ar9285_attach(sc); in athn_attach()
173 else if (AR_SREV_9287(sc)) in athn_attach()
174 error = ar9287_attach(sc); in athn_attach()
175 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) in athn_attach()
176 error = ar9380_attach(sc); in athn_attach()
180 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); in athn_attach()
184 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); in athn_attach()
185 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, in athn_attach()
189 athn_set_power_sleep(sc); in athn_attach()
191 if (!(sc->sc_flags & ATHN_FLAG_USB)) { in athn_attach()
192 sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, in athn_attach()
193 sc); in athn_attach()
194 if (sc->sc_soft_ih == NULL) { in athn_attach()
195 aprint_error_dev(sc->sc_dev, in athn_attach()
200 error = sc->sc_ops.dma_alloc(sc); in athn_attach()
202 aprint_error_dev(sc->sc_dev, in athn_attach()
207 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); in athn_attach()
208 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); in athn_attach()
211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { in athn_attach()
212 DPRINTFN(DBG_INIT, sc, in athn_attach()
214 sc->sc_rfsilent_pin); in athn_attach()
216 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); in athn_attach()
223 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); in athn_attach()
224 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; in athn_attach()
225 if (sc->sc_max_aid != 0) /* we have an override */ in athn_attach()
226 ic->ic_max_aid = sc->sc_max_aid; in athn_attach()
230 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", in athn_attach()
231 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); in athn_attach()
232 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", in athn_attach()
233 sc->sc_txchainmask, sc->sc_rxchainmask); in athn_attach()
236 sc->sc_ntxchains = in athn_attach()
237 ((sc->sc_txchainmask >> 2) & 1) + in athn_attach()
238 ((sc->sc_txchainmask >> 1) & 1) + in athn_attach()
239 ((sc->sc_txchainmask >> 0) & 1); in athn_attach()
240 sc->sc_nrxchains = in athn_attach()
241 ((sc->sc_rxchainmask >> 2) & 1) + in athn_attach()
242 ((sc->sc_rxchainmask >> 1) & 1) + in athn_attach()
243 ((sc->sc_rxchainmask >> 0) & 1); in athn_attach()
245 if (AR_SINGLE_CHIP(sc)) { in athn_attach()
246 aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); in athn_attach()
247 aprint_verbose_dev(sc->sc_dev, in athn_attach()
249 sc->sc_mac_rev, in athn_attach()
250 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, in athn_attach()
253 aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), in athn_attach()
254 athn_get_rf_name(sc)); in athn_attach()
255 aprint_verbose_dev(sc->sc_dev, in athn_attach()
257 sc->sc_mac_rev, in athn_attach()
258 sc->sc_ntxchains, sc->sc_nrxchains, in athn_attach()
259 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); in athn_attach()
262 callout_init(&sc->sc_scan_to, 0); in athn_attach()
263 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); in athn_attach()
264 callout_init(&sc->sc_calib_to, 0); in athn_attach()
265 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); in athn_attach()
267 sc->sc_amrr.amrr_min_success_threshold = 1; in athn_attach()
268 sc->sc_amrr.amrr_max_success_threshold = 15; in athn_attach()
287 if (sc->sc_flags & ATHN_FLAG_11N) { in athn_attach()
296 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) in athn_attach()
298 if (AR_SREV_9380_10_OR_LATER(sc)) in athn_attach()
300 if (AR_SREV_9280_10_OR_LATER(sc)) { in athn_attach()
304 ntxstreams = sc->sc_ntxchains; in athn_attach()
305 nrxstreams = sc->sc_nrxchains; in athn_attach()
306 if (!AR_SREV_9380_10_OR_LATER(sc)) { in athn_attach()
324 if (sc->sc_flags & ATHN_FLAG_11G) { in athn_attach()
330 if (sc->sc_flags & ATHN_FLAG_11A) { in athn_attach()
336 athn_get_chanlist(sc); in athn_attach()
338 ifp->if_softc = sc; in athn_attach()
349 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); in athn_attach()
370 sc->sc_newstate = ic->ic_newstate; in athn_attach()
373 if (sc->sc_media_change == NULL) in athn_attach()
374 sc->sc_media_change = athn_media_change; in athn_attach()
375 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); in athn_attach()
377 athn_radiotap_attach(sc); in athn_attach()
382 athn_detach(struct athn_softc *sc) in athn_detach() argument
384 struct ifnet *ifp = &sc->sc_if; in athn_detach()
387 callout_halt(&sc->sc_scan_to, NULL); in athn_detach()
388 callout_halt(&sc->sc_calib_to, NULL); in athn_detach()
390 if (!(sc->sc_flags & ATHN_FLAG_USB)) { in athn_detach()
392 athn_tx_reclaim(sc, qid); in athn_detach()
395 sc->sc_ops.dma_free(sc); in athn_detach()
397 if (sc->sc_soft_ih != NULL) { in athn_detach()
398 softint_disestablish(sc->sc_soft_ih); in athn_detach()
399 sc->sc_soft_ih = NULL; in athn_detach()
403 if (sc->sc_eep != NULL) { in athn_detach()
404 free(sc->sc_eep, M_DEVBUF); in athn_detach()
405 sc->sc_eep = NULL; in athn_detach()
409 ieee80211_ifdetach(&sc->sc_ic); in athn_detach()
412 callout_destroy(&sc->sc_scan_to); in athn_detach()
413 callout_destroy(&sc->sc_calib_to); in athn_detach()
415 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, in athn_detach()
423 athn_radiotap_attach(struct athn_softc *sc) in athn_radiotap_attach() argument
426 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, in athn_radiotap_attach()
428 &sc->sc_drvbpf); in athn_radiotap_attach()
430 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); in athn_radiotap_attach()
431 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); in athn_radiotap_attach()
432 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); in athn_radiotap_attach()
434 sc->sc_txtap_len = sizeof(sc->sc_txtapu); in athn_radiotap_attach()
435 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); in athn_radiotap_attach()
436 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); in athn_radiotap_attach()
440 athn_get_chanlist(struct athn_softc *sc) in athn_get_chanlist() argument
442 struct ieee80211com *ic = &sc->sc_ic; in athn_get_chanlist()
446 if (sc->sc_flags & ATHN_FLAG_11G) { in athn_get_chanlist()
456 if (sc->sc_flags & ATHN_FLAG_11A) { in athn_get_chanlist()
467 athn_rx_start(struct athn_softc *sc) in athn_rx_start() argument
469 struct ieee80211com *ic = &sc->sc_ic; in athn_rx_start()
473 sc->sc_ops.rx_enable(sc); in athn_rx_start()
487 if (AR_SREV_9280_10_OR_LATER(sc) && in athn_rx_start()
492 athn_set_rxfilter(sc, rfilt); in athn_rx_start()
495 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); in athn_rx_start()
496 AR_WRITE(sc, AR_BSSMSKU, 0xffff); in athn_rx_start()
498 athn_set_opmode(sc); in athn_rx_start()
501 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); in athn_rx_start()
502 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); in athn_rx_start()
504 AR_WRITE(sc, AR_FILT_OFDM, 0); in athn_rx_start()
505 AR_WRITE(sc, AR_FILT_CCK, 0); in athn_rx_start()
506 AR_WRITE(sc, AR_MIBC, 0); in athn_rx_start()
507 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in athn_rx_start()
508 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in athn_rx_start()
511 AR_WRITE(sc, AR_PHY_ERR_1, 0); in athn_rx_start()
512 AR_WRITE(sc, AR_PHY_ERR_2, 0); in athn_rx_start()
515 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); in athn_rx_start()
518 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); in athn_rx_start()
519 AR_WRITE_BARRIER(sc); in athn_rx_start()
523 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) in athn_set_rxfilter() argument
526 AR_WRITE(sc, AR_RX_FILTER, rfilt); in athn_set_rxfilter()
528 reg = AR_READ(sc, AR_PHY_ERR); in athn_set_rxfilter()
531 AR_WRITE(sc, AR_PHY_ERR, reg); in athn_set_rxfilter()
533 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); in athn_set_rxfilter()
535 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); in athn_set_rxfilter()
537 AR_WRITE(sc, AR_PHY_ERR, 0); in athn_set_rxfilter()
538 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); in athn_set_rxfilter()
540 AR_WRITE_BARRIER(sc); in athn_set_rxfilter()
546 struct athn_softc *sc = xsc; in athn_intr() local
547 struct ifnet *ifp = &sc->sc_if; in athn_intr()
552 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) in athn_intr()
559 if (!sc->sc_ops.intr_status(sc)) in athn_intr()
562 AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0); in athn_intr()
563 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); in athn_intr()
564 AR_WRITE_BARRIER(sc); in athn_intr()
566 softint_schedule(sc->sc_soft_ih); in athn_intr()
574 struct athn_softc *sc = xsc; in athn_softintr() local
575 struct ifnet *ifp = &sc->sc_if; in athn_softintr()
580 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) in athn_softintr()
587 sc->sc_ops.intr(sc); in athn_softintr()
589 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); in athn_softintr()
590 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); in athn_softintr()
591 AR_WRITE_BARRIER(sc); in athn_softintr()
595 athn_get_chipid(struct athn_softc *sc) in athn_get_chipid() argument
599 reg = AR_READ(sc, AR_SREV); in athn_get_chipid()
601 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); in athn_get_chipid()
602 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); in athn_get_chipid()
604 sc->sc_flags |= ATHN_FLAG_PCIE; in athn_get_chipid()
606 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); in athn_get_chipid()
607 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); in athn_get_chipid()
608 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) in athn_get_chipid()
609 sc->sc_flags |= ATHN_FLAG_PCIE; in athn_get_chipid()
614 athn_get_mac_name(struct athn_softc *sc) in athn_get_mac_name() argument
617 switch (sc->sc_mac_ver) { in athn_get_mac_name()
645 athn_get_rf_name(struct athn_softc *sc) in athn_get_rf_name() argument
648 KASSERT(!AR_SINGLE_CHIP(sc)); in athn_get_rf_name()
650 switch (sc->sc_rf_rev) { in athn_get_rf_name()
665 athn_reset_power_on(struct athn_softc *sc) in athn_reset_power_on() argument
670 AR_WRITE(sc, AR_RTC_FORCE_WAKE, in athn_reset_power_on()
673 if (!AR_SREV_9380_10_OR_LATER(sc)) { in athn_reset_power_on()
675 AR_WRITE(sc, AR_RC, AR_RC_AHB); in athn_reset_power_on()
678 AR_WRITE(sc, AR_RTC_RESET, 0); in athn_reset_power_on()
679 AR_WRITE_BARRIER(sc); in athn_reset_power_on()
681 if (!AR_SREV_9380_10_OR_LATER(sc)) in athn_reset_power_on()
682 AR_WRITE(sc, AR_RC, 0); in athn_reset_power_on()
683 AR_WRITE(sc, AR_RTC_RESET, 1); in athn_reset_power_on()
687 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == in athn_reset_power_on()
693 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); in athn_reset_power_on()
696 return athn_reset(sc, 0); in athn_reset_power_on()
700 athn_reset(struct athn_softc *sc, int cold_reset) in athn_reset() argument
705 AR_WRITE(sc, AR_RTC_FORCE_WAKE, in athn_reset()
708 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & in athn_reset()
710 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); in athn_reset()
711 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | in athn_reset()
712 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); in athn_reset()
713 } else if (!AR_SREV_9380_10_OR_LATER(sc)) in athn_reset()
714 AR_WRITE(sc, AR_RC, AR_RC_AHB); in athn_reset()
716 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | in athn_reset()
718 AR_WRITE_BARRIER(sc); in athn_reset()
720 AR_WRITE(sc, AR_RTC_RC, 0); in athn_reset()
722 if (!(AR_READ(sc, AR_RTC_RC) & in athn_reset()
728 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); in athn_reset()
731 AR_WRITE(sc, AR_RC, 0); in athn_reset()
732 AR_WRITE_BARRIER(sc); in athn_reset()
737 athn_set_power_awake(struct athn_softc *sc) in athn_set_power_awake() argument
742 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == in athn_set_power_awake()
744 if ((error = athn_reset_power_on(sc)) != 0) in athn_set_power_awake()
746 if (!AR_SREV_9380_10_OR_LATER(sc)) in athn_set_power_awake()
747 athn_init_pll(sc, NULL); in athn_set_power_awake()
749 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in athn_set_power_awake()
750 AR_WRITE_BARRIER(sc); in athn_set_power_awake()
755 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == in athn_set_power_awake()
759 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in athn_set_power_awake()
762 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); in athn_set_power_awake()
766 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in athn_set_power_awake()
767 AR_WRITE_BARRIER(sc); in athn_set_power_awake()
772 athn_set_power_sleep(struct athn_softc *sc) in athn_set_power_sleep() argument
775 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in athn_set_power_sleep()
777 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in athn_set_power_sleep()
778 if (!AR_SREV_9380_10_OR_LATER(sc)) in athn_set_power_sleep()
779 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in athn_set_power_sleep()
784 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) in athn_set_power_sleep()
785 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); in athn_set_power_sleep()
786 AR_WRITE_BARRIER(sc); in athn_set_power_sleep()
790 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) in athn_init_pll() argument
794 if (AR_SREV_9380_10_OR_LATER(sc)) { in athn_init_pll()
795 if (AR_SREV_9485(sc)) in athn_init_pll()
796 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); in athn_init_pll()
799 } else if (AR_SREV_9280_10_OR_LATER(sc)) { in athn_init_pll()
802 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) in athn_init_pll()
804 else if (AR_SREV_9280_20(sc)) in athn_init_pll()
810 } else if (AR_SREV_9160_10_OR_LATER(sc)) { in athn_init_pll()
823 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); in athn_init_pll()
824 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); in athn_init_pll()
825 if (AR_SREV_9271(sc)) { in athn_init_pll()
827 AR_WRITE_BARRIER(sc); in athn_init_pll()
829 AR_WRITE(sc, 0x50050, 0x304); in athn_init_pll()
831 AR_WRITE_BARRIER(sc); in athn_init_pll()
833 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in athn_init_pll()
834 AR_WRITE_BARRIER(sc); in athn_init_pll()
838 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) in athn_write_serdes() argument
844 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); in athn_write_serdes()
845 AR_WRITE_BARRIER(sc); in athn_write_serdes()
849 athn_config_pcie(struct athn_softc *sc) in athn_config_pcie() argument
853 athn_write_serdes(sc, sc->sc_serdes); in athn_config_pcie()
857 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in athn_config_pcie()
860 AR_WRITE(sc, AR_WA, sc->sc_workaround); in athn_config_pcie()
862 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); in athn_config_pcie()
864 AR_WRITE_BARRIER(sc); in athn_config_pcie()
903 athn_config_nonpcie(struct athn_softc *sc) in athn_config_nonpcie() argument
906 athn_write_serdes(sc, &ar_nonpcie_serdes); in athn_config_nonpcie()
910 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, in athn_set_chan() argument
913 struct athn_ops *ops = &sc->sc_ops; in athn_set_chan()
918 if (athn_tx_pending(sc, qid)) in athn_set_chan()
922 if ((error = ops->rf_bus_request(sc)) != 0) in athn_set_chan()
925 ops->set_phy(sc, curchan, extchan); in athn_set_chan()
928 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) in athn_set_chan()
931 sc->sc_curchan = curchan; in athn_set_chan()
932 sc->sc_curchanext = extchan; in athn_set_chan()
935 ops->set_txpower(sc, curchan, extchan); in athn_set_chan()
938 ops->rf_bus_release(sc); in athn_set_chan()
941 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) in athn_set_chan()
942 ops->set_delta_slope(sc, curchan, extchan); in athn_set_chan()
944 ops->spur_mitigate(sc, curchan, extchan); in athn_set_chan()
951 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, in athn_switch_chan() argument
957 athn_disable_interrupts(sc); in athn_switch_chan()
961 athn_stop_tx_dma(sc, qid); in athn_switch_chan()
963 athn_tx_reclaim(sc, qid); in athn_switch_chan()
966 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); in athn_switch_chan()
967 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); in athn_switch_chan()
968 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); in athn_switch_chan()
969 AR_WRITE(sc, AR_FILT_OFDM, 0); in athn_switch_chan()
970 AR_WRITE(sc, AR_FILT_CCK, 0); in athn_switch_chan()
971 athn_set_rxfilter(sc, 0); in athn_switch_chan()
972 error = athn_stop_rx_dma(sc); in athn_switch_chan()
978 if (AR_SREV_9280(sc)) in athn_switch_chan()
983 if (curchan->ic_flags != sc->sc_curchan->ic_flags || in athn_switch_chan()
984 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { in athn_switch_chan()
985 DPRINTFN(DBG_RF, sc, "channel band switch\n"); in athn_switch_chan()
988 error = athn_set_power_awake(sc); in athn_switch_chan()
992 error = athn_set_chan(sc, curchan, extchan); in athn_switch_chan()
995 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); in athn_switch_chan()
996 error = athn_hw_reset(sc, curchan, extchan, 0); in athn_switch_chan()
1000 athn_rx_start(sc); in athn_switch_chan()
1003 athn_enable_interrupts(sc); in athn_switch_chan()
1028 athn_reset_key(struct athn_softc *sc, int entry) in athn_reset_key() argument
1036 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); in athn_reset_key()
1037 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); in athn_reset_key()
1039 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); in athn_reset_key()
1040 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); in athn_reset_key()
1042 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); in athn_reset_key()
1043 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in athn_reset_key()
1045 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); in athn_reset_key()
1046 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); in athn_reset_key()
1048 AR_WRITE_BARRIER(sc); in athn_reset_key()
1056 struct athn_softc *sc = ic->ic_ifp->if_softc; in athn_set_key() local
1100 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); in athn_set_key()
1101 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); in athn_set_key()
1103 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); in athn_set_key()
1104 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); in athn_set_key()
1106 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); in athn_set_key()
1107 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); in athn_set_key()
1109 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); in athn_set_key()
1110 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); in athn_set_key()
1112 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); in athn_set_key()
1113 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); in athn_set_key()
1115 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); in athn_set_key()
1116 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); in athn_set_key()
1126 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); in athn_set_key()
1127 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); in athn_set_key()
1128 AR_WRITE_BARRIER(sc); in athn_set_key()
1136 struct athn_softc *sc = ic->ic_ifp->if_softc; in athn_delete_key() local
1144 athn_reset_key(sc, entry); in athn_delete_key()
1148 athn_reset_key(sc, entry); in athn_delete_key()
1149 athn_reset_key(sc, entry + 64); in athn_delete_key()
1159 athn_led_init(struct athn_softc *sc) in athn_led_init() argument
1161 struct athn_ops *ops = &sc->sc_ops; in athn_led_init()
1163 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); in athn_led_init()
1165 athn_set_led(sc, 0); in athn_led_init()
1169 athn_set_led(struct athn_softc *sc, int on) in athn_set_led() argument
1171 struct athn_ops *ops = &sc->sc_ops; in athn_set_led()
1173 sc->sc_led_state = on; in athn_set_led()
1174 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); in athn_set_led()
1179 athn_btcoex_init(struct athn_softc *sc) in athn_btcoex_init() argument
1181 struct athn_ops *ops = &sc->sc_ops; in athn_btcoex_init()
1184 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { in athn_btcoex_init()
1186 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, in athn_btcoex_init()
1189 AR_SETBITS(sc, sc->sc_gpio_input_en_off, in athn_btcoex_init()
1192 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); in athn_btcoex_init()
1195 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); in athn_btcoex_init()
1196 AR_WRITE_BARRIER(sc); in athn_btcoex_init()
1198 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); in athn_btcoex_init()
1200 AR_SETBITS(sc, sc->sc_gpio_input_en_off, in athn_btcoex_init()
1204 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); in athn_btcoex_init()
1209 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); in athn_btcoex_init()
1210 AR_WRITE_BARRIER(sc); in athn_btcoex_init()
1212 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); in athn_btcoex_init()
1213 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); in athn_btcoex_init()
1218 athn_btcoex_enable(struct athn_softc *sc) in athn_btcoex_enable() argument
1220 struct athn_ops *ops = &sc->sc_ops; in athn_btcoex_enable()
1223 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { in athn_btcoex_enable()
1224 AR_WRITE(sc, AR_BT_COEX_MODE, in athn_btcoex_enable()
1231 AR_WRITE(sc, AR_BT_COEX_WEIGHT, in athn_btcoex_enable()
1234 AR_WRITE(sc, AR_BT_COEX_MODE2, in athn_btcoex_enable()
1238 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); in athn_btcoex_enable()
1239 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); in athn_btcoex_enable()
1240 AR_WRITE_BARRIER(sc); in athn_btcoex_enable()
1242 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, in athn_btcoex_enable()
1246 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, in athn_btcoex_enable()
1249 reg = AR_READ(sc, AR_GPIO_PDPU); in athn_btcoex_enable()
1252 AR_WRITE(sc, AR_GPIO_PDPU, reg); in athn_btcoex_enable()
1253 AR_WRITE_BARRIER(sc); in athn_btcoex_enable()
1256 if (sc->sc_disable_aspm != NULL) in athn_btcoex_enable()
1257 sc->sc_disable_aspm(sc); in athn_btcoex_enable()
1263 athn_btcoex_disable(struct athn_softc *sc) in athn_btcoex_disable() argument
1265 struct athn_ops *ops = &sc->sc_ops; in athn_btcoex_disable()
1267 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); in athn_btcoex_disable()
1269 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, in athn_btcoex_disable()
1272 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { in athn_btcoex_disable()
1273 AR_WRITE(sc, AR_BT_COEX_MODE, in athn_btcoex_disable()
1275 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); in athn_btcoex_disable()
1276 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); in athn_btcoex_disable()
1279 AR_WRITE_BARRIER(sc); in athn_btcoex_disable()
1287 struct athn_softc *sc = arg; in athn_iter_func() local
1290 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); in athn_iter_func()
1296 struct athn_softc *sc = arg; in athn_calib_to() local
1297 struct athn_ops *ops = &sc->sc_ops; in athn_calib_to()
1298 struct ieee80211com *ic = &sc->sc_ic; in athn_calib_to()
1304 if (AR_SREV_9285_11_OR_LATER(sc) && in athn_calib_to()
1305 !AR_SREV_9380_10_OR_LATER(sc) && in athn_calib_to()
1306 (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { in athn_calib_to()
1307 sc->sc_pa_calib_ticks = ticks; in athn_calib_to()
1308 if (AR_SREV_9271(sc)) in athn_calib_to()
1309 ar9271_pa_calib(sc); in athn_calib_to()
1311 ar9285_pa_calib(sc); in athn_calib_to()
1315 if ((sc->sc_flags & ATHN_FLAG_OLPC) && in athn_calib_to()
1316 ticks >= sc->sc_olpc_ticks + 30 * hz) { in athn_calib_to()
1317 sc->sc_olpc_ticks = ticks; in athn_calib_to()
1318 ops->olpc_temp_compensation(sc); in athn_calib_to()
1323 athn_ani_monitor(sc); in athn_calib_to()
1325 ops->next_calib(sc); in athn_calib_to()
1329 athn_iter_func(sc, ic->ic_bss); in athn_calib_to()
1331 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); in athn_calib_to()
1333 callout_schedule(&sc->sc_calib_to, hz / 2); in athn_calib_to()
1338 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, in athn_init_calib() argument
1341 struct athn_ops *ops = &sc->sc_ops; in athn_init_calib()
1344 if (AR_SREV_9380_10_OR_LATER(sc)) in athn_init_calib()
1345 error = ar9003_init_calib(sc); in athn_init_calib()
1346 else if (AR_SREV_9285_10_OR_LATER(sc)) in athn_init_calib()
1347 error = ar9285_init_calib(sc, curchan, extchan); in athn_init_calib()
1349 error = ar5416_init_calib(sc, curchan, extchan); in athn_init_calib()
1353 if (!AR_SREV_9380_10_OR_LATER(sc)) { in athn_init_calib()
1355 if (AR_SREV_9285_11_OR_LATER(sc)) { in athn_init_calib()
1356 sc->sc_pa_calib_ticks = ticks; in athn_init_calib()
1357 if (AR_SREV_9271(sc)) in athn_init_calib()
1358 ar9271_pa_calib(sc); in athn_init_calib()
1360 ar9285_pa_calib(sc); in athn_init_calib()
1363 ops->noisefloor_calib(sc); in athn_init_calib()
1365 if (AR_SREV_9160_10_OR_LATER(sc)) { in athn_init_calib()
1367 sc->sc_sup_calib_mask = ATHN_CAL_IQ; in athn_init_calib()
1368 if (AR_SREV_9380_10_OR_LATER(sc)) { in athn_init_calib()
1370 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; in athn_init_calib()
1376 if (!AR_SREV_9287(sc)) { in athn_init_calib()
1378 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; in athn_init_calib()
1381 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; in athn_init_calib()
1392 athn_ani_get_rssi(struct athn_softc *sc) in athn_ani_get_rssi() argument
1401 athn_ani_ofdm_err_trigger(struct athn_softc *sc) in athn_ani_ofdm_err_trigger() argument
1403 struct athn_ani *ani = &sc->sc_ani; in athn_ani_ofdm_err_trigger()
1404 struct athn_ops *ops = &sc->sc_ops; in athn_ani_ofdm_err_trigger()
1410 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); in athn_ani_ofdm_err_trigger()
1417 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); in athn_ani_ofdm_err_trigger()
1422 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { in athn_ani_ofdm_err_trigger()
1425 ops->set_firstep_level(sc, ani->firstep_level); in athn_ani_ofdm_err_trigger()
1430 rssi = athn_ani_get_rssi(sc); in athn_ani_ofdm_err_trigger()
1438 ops->disable_ofdm_weak_signal(sc); in athn_ani_ofdm_err_trigger()
1440 ops->set_spur_immunity_level(sc, 0); in athn_ani_ofdm_err_trigger()
1443 ops->set_firstep_level(sc, ani->firstep_level); in athn_ani_ofdm_err_trigger()
1452 ops->enable_ofdm_weak_signal(sc); in athn_ani_ofdm_err_trigger()
1456 ops->set_firstep_level(sc, ani->firstep_level); in athn_ani_ofdm_err_trigger()
1458 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { in athn_ani_ofdm_err_trigger()
1466 ops->disable_ofdm_weak_signal(sc); in athn_ani_ofdm_err_trigger()
1470 ops->set_firstep_level(sc, 0); in athn_ani_ofdm_err_trigger()
1478 athn_ani_cck_err_trigger(struct athn_softc *sc) in athn_ani_cck_err_trigger() argument
1480 struct athn_ani *ani = &sc->sc_ani; in athn_ani_cck_err_trigger()
1481 struct athn_ops *ops = &sc->sc_ops; in athn_ani_cck_err_trigger()
1487 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); in athn_ani_cck_err_trigger()
1492 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { in athn_ani_cck_err_trigger()
1495 ops->set_firstep_level(sc, ani->firstep_level); in athn_ani_cck_err_trigger()
1500 rssi = athn_ani_get_rssi(sc); in athn_ani_cck_err_trigger()
1508 ops->set_firstep_level(sc, ani->firstep_level); in athn_ani_cck_err_trigger()
1510 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { in athn_ani_cck_err_trigger()
1517 ops->set_firstep_level(sc, 0); in athn_ani_cck_err_trigger()
1525 athn_ani_lower_immunity(struct athn_softc *sc) in athn_ani_lower_immunity() argument
1527 struct athn_ani *ani = &sc->sc_ani; in athn_ani_lower_immunity()
1528 struct athn_ops *ops = &sc->sc_ops; in athn_ani_lower_immunity()
1532 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { in athn_ani_lower_immunity()
1535 ops->set_firstep_level(sc, ani->firstep_level); in athn_ani_lower_immunity()
1540 rssi = athn_ani_get_rssi(sc); in athn_ani_lower_immunity()
1553 ops->enable_ofdm_weak_signal(sc); in athn_ani_lower_immunity()
1558 ops->set_firstep_level(sc, ani->firstep_level); in athn_ani_lower_immunity()
1565 ops->set_firstep_level(sc, ani->firstep_level); in athn_ani_lower_immunity()
1575 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); in athn_ani_lower_immunity()
1578 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); in athn_ani_lower_immunity()
1585 athn_ani_restart(struct athn_softc *sc) in athn_ani_restart() argument
1587 struct athn_ani *ani = &sc->sc_ani; in athn_ani_restart()
1589 AR_WRITE(sc, AR_PHY_ERR_1, 0); in athn_ani_restart()
1590 AR_WRITE(sc, AR_PHY_ERR_2, 0); in athn_ani_restart()
1591 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in athn_ani_restart()
1592 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in athn_ani_restart()
1593 AR_WRITE_BARRIER(sc); in athn_ani_restart()
1603 athn_ani_monitor(struct athn_softc *sc) in athn_ani_monitor() argument
1605 struct athn_ani *ani = &sc->sc_ani; in athn_ani_monitor()
1610 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ in athn_ani_monitor()
1611 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ in athn_ani_monitor()
1612 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ in athn_ani_monitor()
1620 (athn_clock_rate(sc) * 1000); in athn_ani_monitor()
1629 athn_ani_restart(sc); in athn_ani_monitor()
1634 phy1 = AR_READ(sc, AR_PHY_ERR_1); in athn_ani_monitor()
1635 phy2 = AR_READ(sc, AR_PHY_ERR_2); in athn_ani_monitor()
1638 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); in athn_ani_monitor()
1639 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in athn_ani_monitor()
1642 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); in athn_ani_monitor()
1643 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in athn_ani_monitor()
1646 AR_WRITE_BARRIER(sc); in athn_ani_monitor()
1658 athn_ani_lower_immunity(sc); in athn_ani_monitor()
1659 athn_ani_restart(sc); in athn_ani_monitor()
1665 athn_ani_ofdm_err_trigger(sc); in athn_ani_monitor()
1666 athn_ani_restart(sc); in athn_ani_monitor()
1669 athn_ani_cck_err_trigger(sc); in athn_ani_monitor()
1670 athn_ani_restart(sc); in athn_ani_monitor()
1715 athn_init_dma(struct athn_softc *sc) in athn_init_dma() argument
1719 if (!AR_SREV_9380_10_OR_LATER(sc)) { in athn_init_dma()
1721 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in athn_init_dma()
1723 reg = AR_READ(sc, AR_TXCFG); in athn_init_dma()
1728 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) in athn_init_dma()
1730 else if (!AR_SREV_9380_10_OR_LATER(sc)) in athn_init_dma()
1732 AR_WRITE(sc, AR_TXCFG, reg); in athn_init_dma()
1735 reg = AR_READ(sc, AR_RXCFG); in athn_init_dma()
1737 AR_WRITE(sc, AR_RXCFG, reg); in athn_init_dma()
1740 AR_WRITE(sc, AR_RXFIFO_CFG, 512); in athn_init_dma()
1743 if (AR_SREV_9285(sc)) { in athn_init_dma()
1744 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, in athn_init_dma()
1746 } else if (!AR_SREV_9271(sc)) { in athn_init_dma()
1747 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, in athn_init_dma()
1750 AR_WRITE_BARRIER(sc); in athn_init_dma()
1753 if (AR_SREV_9380_10_OR_LATER(sc)) in athn_init_dma()
1754 ar9003_reset_txsring(sc); in athn_init_dma()
1758 athn_inc_tx_trigger_level(struct athn_softc *sc) in athn_inc_tx_trigger_level() argument
1762 reg = AR_READ(sc, AR_TXCFG); in athn_inc_tx_trigger_level()
1768 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) in athn_inc_tx_trigger_level()
1771 AR_WRITE(sc, AR_TXCFG, reg); in athn_inc_tx_trigger_level()
1772 AR_WRITE_BARRIER(sc); in athn_inc_tx_trigger_level()
1776 athn_stop_rx_dma(struct athn_softc *sc) in athn_stop_rx_dma() argument
1780 AR_WRITE(sc, AR_CR, AR_CR_RXD); in athn_stop_rx_dma()
1783 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) in athn_stop_rx_dma()
1787 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); in athn_stop_rx_dma()
1793 athn_rx_abort(struct athn_softc *sc) in athn_rx_abort() argument
1797 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); in athn_rx_abort()
1799 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) in athn_rx_abort()
1803 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); in athn_rx_abort()
1804 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); in athn_rx_abort()
1805 AR_WRITE_BARRIER(sc); in athn_rx_abort()
1811 athn_tx_reclaim(struct athn_softc *sc, int qid) in athn_tx_reclaim() argument
1813 struct athn_txq *txq = &sc->sc_txq[qid]; in athn_tx_reclaim()
1821 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, in athn_tx_reclaim()
1823 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); in athn_tx_reclaim()
1829 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); in athn_tx_reclaim()
1834 athn_tx_pending(struct athn_softc *sc, int qid) in athn_tx_pending() argument
1837 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || in athn_tx_pending()
1838 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; in athn_tx_pending()
1842 athn_stop_tx_dma(struct athn_softc *sc, int qid) in athn_stop_tx_dma() argument
1847 AR_WRITE(sc, AR_Q_TXD, 1 << qid); in athn_stop_tx_dma()
1849 if (!athn_tx_pending(sc, qid)) in athn_stop_tx_dma()
1855 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; in athn_stop_tx_dma()
1856 AR_WRITE(sc, AR_QUIET2, in athn_stop_tx_dma()
1858 AR_WRITE(sc, AR_QUIET_PERIOD, 100); in athn_stop_tx_dma()
1859 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); in athn_stop_tx_dma()
1860 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); in athn_stop_tx_dma()
1861 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) in athn_stop_tx_dma()
1864 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in athn_stop_tx_dma()
1865 AR_WRITE_BARRIER(sc); in athn_stop_tx_dma()
1867 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); in athn_stop_tx_dma()
1868 AR_WRITE_BARRIER(sc); in athn_stop_tx_dma()
1871 if (!athn_tx_pending(sc, qid)) in athn_stop_tx_dma()
1876 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in athn_stop_tx_dma()
1878 AR_WRITE(sc, AR_Q_TXD, 0); in athn_stop_tx_dma()
1879 AR_WRITE_BARRIER(sc); in athn_stop_tx_dma()
1883 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) in athn_txtime() argument
1906 athn_init_tx_queues(struct athn_softc *sc) in athn_init_tx_queues() argument
1911 SIMPLEQ_INIT(&sc->sc_txq[qid].head); in athn_init_tx_queues()
1912 sc->sc_txq[qid].lastds = NULL; in athn_init_tx_queues()
1913 sc->sc_txq[qid].wait = NULL; in athn_init_tx_queues()
1914 sc->sc_txq[qid].queued = 0; in athn_init_tx_queues()
1916 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), in athn_init_tx_queues()
1920 AR_WRITE(sc, AR_QMISC(qid), in athn_init_tx_queues()
1922 AR_WRITE(sc, AR_DMISC(qid), in athn_init_tx_queues()
1928 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), in athn_init_tx_queues()
1931 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), in athn_init_tx_queues()
1936 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), in athn_init_tx_queues()
1942 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), in athn_init_tx_queues()
1945 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), in athn_init_tx_queues()
1950 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), in athn_init_tx_queues()
1954 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), in athn_init_tx_queues()
1957 if (AR_SREV_9380_10_OR_LATER(sc)) { in athn_init_tx_queues()
1959 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); in athn_init_tx_queues()
1962 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); in athn_init_tx_queues()
1964 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); in athn_init_tx_queues()
1965 AR_WRITE_BARRIER(sc); in athn_init_tx_queues()
1969 athn_set_sta_timers(struct athn_softc *sc) in athn_set_sta_timers() argument
1971 struct ieee80211com *ic = &sc->sc_ic; in athn_set_sta_timers()
1976 tsfhi = AR_READ(sc, AR_TSF_U32); in athn_set_sta_timers()
1977 tsflo = AR_READ(sc, AR_TSF_L32); in athn_set_sta_timers()
2000 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); in athn_set_sta_timers()
2001 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); in athn_set_sta_timers()
2002 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); in athn_set_sta_timers()
2008 reg = AR_READ(sc, AR_RSSI_THR); in athn_set_sta_timers()
2010 AR_WRITE(sc, AR_RSSI_THR, reg); in athn_set_sta_timers()
2012 AR_WRITE(sc, AR_NEXT_DTIM, in athn_set_sta_timers()
2014 AR_WRITE(sc, AR_NEXT_TIM, in athn_set_sta_timers()
2018 AR_WRITE(sc, AR_SLEEP1, in athn_set_sta_timers()
2021 AR_WRITE(sc, AR_SLEEP2, in athn_set_sta_timers()
2024 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); in athn_set_sta_timers()
2025 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); in athn_set_sta_timers()
2027 AR_SETBITS(sc, AR_TIMER_MODE, in athn_set_sta_timers()
2031 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); in athn_set_sta_timers()
2033 AR_WRITE_BARRIER(sc); in athn_set_sta_timers()
2038 athn_set_hostap_timers(struct athn_softc *sc) in athn_set_hostap_timers() argument
2040 struct ieee80211com *ic = &sc->sc_ic; in athn_set_hostap_timers()
2047 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); in athn_set_hostap_timers()
2048 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, in athn_set_hostap_timers()
2050 AR_WRITE(sc, AR_NEXT_CFP, in athn_set_hostap_timers()
2053 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); in athn_set_hostap_timers()
2054 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); in athn_set_hostap_timers()
2055 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); in athn_set_hostap_timers()
2056 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); in athn_set_hostap_timers()
2058 AR_WRITE(sc, AR_TIMER_MODE, in athn_set_hostap_timers()
2061 AR_WRITE_BARRIER(sc); in athn_set_hostap_timers()
2066 athn_set_opmode(struct athn_softc *sc) in athn_set_opmode() argument
2070 switch (sc->sc_ic.ic_opmode) { in athn_set_opmode()
2073 reg = AR_READ(sc, AR_STA_ID1); in athn_set_opmode()
2076 AR_WRITE(sc, AR_STA_ID1, reg); in athn_set_opmode()
2078 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in athn_set_opmode()
2082 reg = AR_READ(sc, AR_STA_ID1); in athn_set_opmode()
2085 AR_WRITE(sc, AR_STA_ID1, reg); in athn_set_opmode()
2087 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in athn_set_opmode()
2091 reg = AR_READ(sc, AR_STA_ID1); in athn_set_opmode()
2094 AR_WRITE(sc, AR_STA_ID1, reg); in athn_set_opmode()
2097 AR_WRITE_BARRIER(sc); in athn_set_opmode()
2101 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) in athn_set_bss() argument
2105 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); in athn_set_bss()
2106 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | in athn_set_bss()
2108 AR_WRITE_BARRIER(sc); in athn_set_bss()
2112 athn_enable_interrupts(struct athn_softc *sc) in athn_enable_interrupts() argument
2116 athn_disable_interrupts(sc); /* XXX */ in athn_enable_interrupts()
2118 AR_WRITE(sc, AR_IMR, sc->sc_imask); in athn_enable_interrupts()
2120 mask2 = AR_READ(sc, AR_IMR_S2); in athn_enable_interrupts()
2124 AR_WRITE(sc, AR_IMR_S2, mask2); in athn_enable_interrupts()
2126 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in athn_enable_interrupts()
2128 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); in athn_enable_interrupts()
2130 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); in athn_enable_interrupts()
2131 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); in athn_enable_interrupts()
2133 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); in athn_enable_interrupts()
2134 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); in athn_enable_interrupts()
2135 AR_WRITE_BARRIER(sc); in athn_enable_interrupts()
2139 athn_disable_interrupts(struct athn_softc *sc) in athn_disable_interrupts() argument
2142 AR_WRITE(sc, AR_IER, 0); in athn_disable_interrupts()
2143 (void)AR_READ(sc, AR_IER); in athn_disable_interrupts()
2145 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); in athn_disable_interrupts()
2146 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); in athn_disable_interrupts()
2148 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); in athn_disable_interrupts()
2149 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); in athn_disable_interrupts()
2151 AR_WRITE(sc, AR_IMR, 0); in athn_disable_interrupts()
2153 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | in athn_disable_interrupts()
2157 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in athn_disable_interrupts()
2158 AR_WRITE_BARRIER(sc); in athn_disable_interrupts()
2162 athn_init_qos(struct athn_softc *sc) in athn_init_qos() argument
2166 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); in athn_init_qos()
2167 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); in athn_init_qos()
2168 AR_WRITE(sc, AR_QOS_NO_ACK, in athn_init_qos()
2172 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); in athn_init_qos()
2174 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); in athn_init_qos()
2175 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); in athn_init_qos()
2176 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); in athn_init_qos()
2177 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); in athn_init_qos()
2178 AR_WRITE_BARRIER(sc); in athn_init_qos()
2182 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, in athn_hw_reset() argument
2185 struct ieee80211com *ic = &sc->sc_ic; in athn_hw_reset()
2186 struct athn_ops *ops = &sc->sc_ops; in athn_hw_reset()
2191 if ((error = athn_set_power_awake(sc)) != 0) { in athn_hw_reset()
2192 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); in athn_hw_reset()
2197 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) in athn_hw_reset()
2200 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; in athn_hw_reset()
2201 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | in athn_hw_reset()
2206 ops->disable_phy(sc); in athn_hw_reset()
2208 if (init && AR_SREV_9271(sc)) { in athn_hw_reset()
2209 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, in athn_hw_reset()
2213 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { in athn_hw_reset()
2215 tsfhi = AR_READ(sc, AR_TSF_U32); in athn_hw_reset()
2216 tsflo = AR_READ(sc, AR_TSF_L32); in athn_hw_reset()
2219 error = athn_reset_power_on(sc); in athn_hw_reset()
2222 error = athn_reset(sc, 0); in athn_hw_reset()
2225 aprint_error_dev(sc->sc_dev, in athn_hw_reset()
2231 if ((error = athn_set_power_awake(sc)) != 0) { in athn_hw_reset()
2232 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); in athn_hw_reset()
2236 athn_init_pll(sc, curchan); in athn_hw_reset()
2237 ops->set_rf_mode(sc, curchan); in athn_hw_reset()
2239 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { in athn_hw_reset()
2241 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); in athn_hw_reset()
2242 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) in athn_hw_reset()
2245 aprint_error_dev(sc->sc_dev, in athn_hw_reset()
2250 if (init && AR_SREV_9271(sc)) { in athn_hw_reset()
2251 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, in athn_hw_reset()
2255 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { in athn_hw_reset()
2257 AR_WRITE(sc, AR_TSF_L32, tsflo); in athn_hw_reset()
2258 AR_WRITE(sc, AR_TSF_U32, tsfhi); in athn_hw_reset()
2261 if (AR_SREV_9280_10_OR_LATER(sc)) in athn_hw_reset()
2262 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); in athn_hw_reset()
2264 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) in athn_hw_reset()
2265 ar9287_1_3_enable_async_fifo(sc); in athn_hw_reset()
2268 ops->hw_init(sc, curchan, extchan); in athn_hw_reset()
2274 if (AR_SREV_9280_20_OR_LATER(sc)) { in athn_hw_reset()
2275 reg = AR_READ(sc, AR_AES_MUTE_MASK1); in athn_hw_reset()
2281 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); in athn_hw_reset()
2282 } else if (AR_SREV_9160_10_OR_LATER(sc)) { in athn_hw_reset()
2284 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, in athn_hw_reset()
2286 AR_SETBITS(sc, AR_PCU_MISC_MODE2, in athn_hw_reset()
2291 ops->set_delta_slope(sc, curchan, extchan); in athn_hw_reset()
2293 ops->spur_mitigate(sc, curchan, extchan); in athn_hw_reset()
2294 ops->init_from_rom(sc, curchan, extchan); in athn_hw_reset()
2297 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); in athn_hw_reset()
2298 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | in athn_hw_reset()
2301 athn_set_opmode(sc); in athn_hw_reset()
2303 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); in athn_hw_reset()
2304 AR_WRITE(sc, AR_BSSMSKU, 0xffff); in athn_hw_reset()
2307 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); in athn_hw_reset()
2309 AR_WRITE(sc, AR_BSS_ID0, 0); in athn_hw_reset()
2310 AR_WRITE(sc, AR_BSS_ID1, 0); in athn_hw_reset()
2312 AR_WRITE(sc, AR_ISR, 0xffffffff); in athn_hw_reset()
2314 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); in athn_hw_reset()
2316 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { in athn_hw_reset()
2317 aprint_error_dev(sc->sc_dev, "could not set channel\n"); in athn_hw_reset()
2320 sc->sc_curchan = curchan; in athn_hw_reset()
2321 sc->sc_curchanext = extchan; in athn_hw_reset()
2324 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); in athn_hw_reset()
2326 athn_init_tx_queues(sc); in athn_hw_reset()
2329 sc->sc_imask = in athn_hw_reset()
2334 if (AR_SREV_9380_10_OR_LATER(sc)) in athn_hw_reset()
2335 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; in athn_hw_reset()
2338 sc->sc_imask |= AR_IMR_MIB; in athn_hw_reset()
2340 AR_WRITE(sc, AR_IMR, sc->sc_imask); in athn_hw_reset()
2341 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); in athn_hw_reset()
2342 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); in athn_hw_reset()
2343 sc->sc_isync = AR_INTR_SYNC_DEFAULT; in athn_hw_reset()
2344 if (sc->sc_flags & ATHN_FLAG_RFSILENT) in athn_hw_reset()
2345 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); in athn_hw_reset()
2346 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); in athn_hw_reset()
2347 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); in athn_hw_reset()
2348 if (AR_SREV_9380_10_OR_LATER(sc)) { in athn_hw_reset()
2349 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); in athn_hw_reset()
2350 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); in athn_hw_reset()
2351 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); in athn_hw_reset()
2352 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); in athn_hw_reset()
2355 athn_init_qos(sc); in athn_hw_reset()
2357 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); in athn_hw_reset()
2359 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) in athn_hw_reset()
2360 ar9287_1_3_setup_async_fifo(sc); in athn_hw_reset()
2363 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in athn_hw_reset()
2365 athn_init_dma(sc); in athn_hw_reset()
2368 AR_WRITE(sc, sc->sc_obs_off, 8); in athn_hw_reset()
2371 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); in athn_hw_reset()
2373 ops->init_baseband(sc); in athn_hw_reset()
2375 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { in athn_hw_reset()
2376 aprint_error_dev(sc->sc_dev, in athn_hw_reset()
2381 ops->set_rxchains(sc); in athn_hw_reset()
2383 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); in athn_hw_reset()
2385 if (sc->sc_flags & ATHN_FLAG_USB) { in athn_hw_reset()
2386 if (AR_SREV_9271(sc)) in athn_hw_reset()
2387 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in athn_hw_reset()
2389 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in athn_hw_reset()
2394 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in athn_hw_reset()
2397 AR_WRITE_BARRIER(sc); in athn_hw_reset()
2414 struct athn_softc *sc = ic->ic_ifp->if_softc; in athn_newassoc() local
2420 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); in athn_newassoc()
2432 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); in athn_newassoc()
2443 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", in athn_newassoc()
2451 struct athn_softc *sc = ifp->if_softc; in athn_media_change() local
2452 struct ieee80211com *ic = &sc->sc_ic; in athn_media_change()
2467 sc->sc_fixed_ridx = ridx; in athn_media_change()
2479 struct athn_softc *sc = arg; in athn_next_scan() local
2480 struct ieee80211com *ic = &sc->sc_ic; in athn_next_scan()
2493 struct athn_softc *sc = ifp->if_softc; in athn_newstate() local
2497 callout_stop(&sc->sc_calib_to); in athn_newstate()
2501 athn_set_led(sc, 0); in athn_newstate()
2505 athn_set_led(sc, !sc->sc_led_state); in athn_newstate()
2506 error = athn_switch_chan(sc, ic->ic_curchan, NULL); in athn_newstate()
2509 callout_schedule(&sc->sc_scan_to, hz / 5); in athn_newstate()
2512 athn_set_led(sc, 0); in athn_newstate()
2513 error = athn_switch_chan(sc, ic->ic_curchan, NULL); in athn_newstate()
2520 athn_set_led(sc, 1); in athn_newstate()
2528 athn_set_bss(sc, ic->ic_bss); in athn_newstate()
2529 athn_disable_interrupts(sc); in athn_newstate()
2532 athn_set_hostap_timers(sc); in athn_newstate()
2534 sc->sc_imask |= AR_IMR_SWBA; in athn_newstate()
2538 athn_set_sta_timers(sc); in athn_newstate()
2540 sc->sc_imask |= AR_IMR_BMISS; in athn_newstate()
2543 reg = AR_READ(sc, AR_RX_FILTER); in athn_newstate()
2546 AR_WRITE(sc, AR_RX_FILTER, reg); in athn_newstate()
2547 AR_WRITE_BARRIER(sc); in athn_newstate()
2549 athn_enable_interrupts(sc); in athn_newstate()
2551 if (sc->sc_sup_calib_mask != 0) { in athn_newstate()
2552 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); in athn_newstate()
2553 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; in athn_newstate()
2558 callout_schedule(&sc->sc_calib_to, hz / 2); in athn_newstate()
2562 return sc->sc_newstate(ic, nstate, arg); in athn_newstate()
2570 struct athn_softc *sc = ic->ic_ifp->if_softc; in athn_updateedca() local
2578 AR_WRITE(sc, AR_DLCL_IFS(qid), in athn_updateedca()
2583 AR_WRITE(sc, AR_DCHNTIME(qid), in athn_updateedca()
2588 AR_WRITE(sc, AR_DCHNTIME(qid), 0); in athn_updateedca()
2590 AR_WRITE_BARRIER(sc); in athn_updateedca()
2596 athn_clock_rate(struct athn_softc *sc) in athn_clock_rate() argument
2598 struct ieee80211com *ic = &sc->sc_ic; in athn_clock_rate()
2602 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) in athn_clock_rate()
2611 if (sc->sc_curchanext != NULL) in athn_clock_rate()
2620 struct athn_softc *sc = ifp->if_softc; in athn_updateslot() local
2621 struct ieee80211com *ic = &sc->sc_ic; in athn_updateslot()
2625 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); in athn_updateslot()
2626 AR_WRITE_BARRIER(sc); in athn_updateslot()
2632 struct athn_softc *sc = ifp->if_softc; in athn_start() local
2633 struct ieee80211com *ic = &sc->sc_ic; in athn_start()
2639 || !device_is_active(sc->sc_dev)) in athn_start()
2643 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { in athn_start()
2681 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { in athn_start()
2687 sc->sc_tx_timer = 5; in athn_start()
2695 struct athn_softc *sc = ifp->if_softc; in athn_watchdog() local
2699 if (sc->sc_tx_timer > 0) { in athn_watchdog()
2700 if (--sc->sc_tx_timer == 0) { in athn_watchdog()
2701 aprint_error_dev(sc->sc_dev, "device timeout\n"); in athn_watchdog()
2710 ieee80211_watchdog(&sc->sc_ic); in athn_watchdog()
2714 athn_set_multi(struct athn_softc *sc) in athn_set_multi() argument
2716 struct ethercom *ec = &sc->sc_ec; in athn_set_multi()
2753 AR_WRITE(sc, AR_MCAST_FIL0, lo); in athn_set_multi()
2754 AR_WRITE(sc, AR_MCAST_FIL1, hi); in athn_set_multi()
2755 AR_WRITE_BARRIER(sc); in athn_set_multi()
2761 struct athn_softc *sc = ifp->if_softc; in athn_ioctl() local
2762 struct ieee80211com *ic = &sc->sc_ic; in athn_ioctl()
2775 if (((ifp->if_flags ^ sc->sc_if_flags) & in athn_ioctl()
2791 sc->sc_if_flags = ifp->if_flags; in athn_ioctl()
2798 athn_set_multi(sc); in athn_ioctl()
2808 athn_switch_chan(sc, ic->ic_curchan, NULL); in athn_ioctl()
2833 struct athn_softc *sc = ifp->if_softc; in athn_init() local
2834 struct athn_ops *ops = &sc->sc_ops; in athn_init()
2835 struct ieee80211com *ic = &sc->sc_ic; in athn_init()
2842 if (device_is_active(sc->sc_dev)) { in athn_init()
2848 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || in athn_init()
2849 !device_is_active(sc->sc_dev)) { in athn_init()
2851 device_xname(sc->sc_dev)); in athn_init()
2865 if (sc->sc_enable != NULL) { in athn_init()
2866 if ((error = sc->sc_enable(sc)) != 0) { in athn_init()
2867 aprint_error_dev(sc->sc_dev, in athn_init()
2871 if ((error = athn_reset_power_on(sc)) != 0) { in athn_init()
2872 aprint_error_dev(sc->sc_dev, in athn_init()
2878 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) in athn_init()
2879 athn_config_nonpcie(sc); in athn_init()
2881 athn_config_pcie(sc); in athn_init()
2884 for (i = 0; i < sc->sc_kc_entries; i++) in athn_init()
2885 athn_reset_key(sc, i); in athn_init()
2887 ops->enable_antenna_diversity(sc); in athn_init()
2891 if (sc->sc_flags & ATHN_FLAG_BTCOEX) in athn_init()
2892 athn_btcoex_init(sc); in athn_init()
2896 athn_led_init(sc); in athn_init()
2899 if (sc->sc_flags & ATHN_FLAG_RFSILENT) in athn_init()
2900 ops->rfsilent_init(sc); in athn_init()
2902 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { in athn_init()
2903 aprint_error_dev(sc->sc_dev, in athn_init()
2909 athn_rx_start(sc); in athn_init()
2912 athn_enable_interrupts(sc); in athn_init()
2916 if (sc->sc_flags & ATHN_FLAG_BTCOEX) in athn_init()
2917 athn_btcoex_enable(sc); in athn_init()
2944 struct athn_softc *sc = ifp->if_softc; in athn_stop() local
2945 struct ieee80211com *ic = &sc->sc_ic; in athn_stop()
2948 ifp->if_timer = sc->sc_tx_timer = 0; in athn_stop()
2951 callout_stop(&sc->sc_scan_to); in athn_stop()
2959 if (sc->sc_flags & ATHN_FLAG_BTCOEX) in athn_stop()
2960 athn_btcoex_disable(sc); in athn_stop()
2964 athn_disable_interrupts(sc); in athn_stop()
2966 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); in athn_stop()
2967 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); in athn_stop()
2970 athn_stop_tx_dma(sc, qid); in athn_stop()
2973 athn_tx_reclaim(sc, qid); in athn_stop()
2976 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); in athn_stop()
2977 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); in athn_stop()
2978 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); in athn_stop()
2979 AR_WRITE(sc, AR_FILT_OFDM, 0); in athn_stop()
2980 AR_WRITE(sc, AR_FILT_CCK, 0); in athn_stop()
2981 AR_WRITE_BARRIER(sc); in athn_stop()
2982 athn_set_rxfilter(sc, 0); in athn_stop()
2983 athn_stop_rx_dma(sc); in athn_stop()
2985 athn_reset(sc, 0); in athn_stop()
2986 athn_init_pll(sc, NULL); in athn_stop()
2987 athn_set_power_awake(sc); in athn_stop()
2988 athn_reset(sc, 1); in athn_stop()
2989 athn_init_pll(sc, NULL); in athn_stop()
2991 athn_set_power_sleep(sc); in athn_stop()
2995 if (disable && sc->sc_disable != NULL) in athn_stop()
2996 sc->sc_disable(sc); in athn_stop()
2999 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); in athn_stop()
3005 struct athn_softc *sc = device_private(self); in athn_pmf_wlan_off() local
3006 struct ifnet *ifp = &sc->sc_if; in athn_pmf_wlan_off()
3014 athn_suspend(struct athn_softc *sc) in athn_suspend() argument
3016 struct ifnet *ifp = &sc->sc_if; in athn_suspend()
3023 athn_resume(struct athn_softc *sc) in athn_resume() argument
3025 struct ifnet *ifp = &sc->sc_if; in athn_resume()