Lines Matching refs:eep

133 	struct ar9380_eeprom *eep = sc->sc_eep;  in ar9380_setup()  local
134 struct ar9380_base_eep_hdr *base = &eep->baseEepHeader; in ar9380_setup()
144 IEEE80211_ADDR_COPY(ic->ic_myaddr, eep->macAddr); in ar9380_setup()
179 type = MS(eep->baseEepHeader.txrxgain, AR_EEP_RX_GAIN); in ar9380_setup()
190 type = MS(eep->baseEepHeader.txrxgain, AR_EEP_TX_GAIN); in ar9380_setup()
221 struct ar9380_eeprom *eep = sc->sc_eep; in ar9380_swap_rom() local
222 struct ar9380_base_eep_hdr *base = &eep->baseEepHeader; in ar9380_swap_rom()
230 modal = &eep->modalHeader2G; in ar9380_swap_rom()
238 modal = &eep->modalHeader5G; in ar9380_swap_rom()
252 const struct ar9380_eeprom *eep = sc->sc_eep; in ar9380_get_paprd_masks() local
256 modal = &eep->modalHeader2G; in ar9380_get_paprd_masks()
258 modal = &eep->modalHeader5G; in ar9380_get_paprd_masks()
303 const struct ar9380_eeprom *eep = sc->sc_eep; in ar9380_init_from_rom() local
310 modal = &eep->modalHeader2G; in ar9380_init_from_rom()
312 modal = &eep->modalHeader5G; in ar9380_init_from_rom()
349 ant_div_ctrl = eep->base_ext1.ant_div_control; in ar9380_init_from_rom()
366 if (eep->baseEepHeader.miscConfiguration & AR_EEP_DRIVE_STRENGTH) { in ar9380_init_from_rom()
400 eep->base_ext2.xatten1DBLow[i] != 0) { in ar9380_init_from_rom()
403 5180, eep->base_ext2.xatten1DBLow[i], in ar9380_init_from_rom()
409 5785, eep->base_ext2.xatten1DBHigh[i]); in ar9380_init_from_rom()
415 eep->base_ext2.xatten1MarginLow[i] != 0) { in ar9380_init_from_rom()
418 5180, eep->base_ext2.xatten1MarginLow[i], in ar9380_init_from_rom()
424 5785, eep->base_ext2.xatten1MarginHigh[i]); in ar9380_init_from_rom()
443 (eep->baseEepHeader.featureEnable & AR_EEP_TUNING_CAPS)) { in ar9380_init_from_rom()
446 eep->baseEepHeader.params_for_tuning_caps[0]); in ar9380_init_from_rom()
448 eep->baseEepHeader.params_for_tuning_caps[0]); in ar9380_init_from_rom()
458 const struct ar9380_eeprom *eep = sc->sc_eep; in ar9380_init_swreg() local
460 if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) { in ar9380_init_swreg()
464 AR_WRITE(sc, AR_RTC_REG_CONTROL0, eep->baseEepHeader.swreg); in ar9380_init_swreg()
494 const struct ar9380_eeprom *eep = sc->sc_eep; in ar9485_init_swreg() local
500 if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) { in ar9485_init_swreg()
564 const struct ar9380_eeprom *eep = sc->sc_eep; in ar9380_spur_mitigate_ofdm() local
571 spurchans = eep->modalHeader2G.spurChans; in ar9380_spur_mitigate_ofdm()
573 spurchans = eep->modalHeader5G.spurChans; in ar9380_spur_mitigate_ofdm()
720 const struct ar9380_eeprom *eep = sc->sc_eep; in ar9380_set_txpower() local
728 eep->calTargetFbinCck, eep->calTargetPowerCck, in ar9380_set_txpower()
733 eep->calTargetFbin2G, eep->calTargetPower2G, in ar9380_set_txpower()
738 eep->calTargetFbin2GHT20, eep->calTargetPower2GHT20, in ar9380_set_txpower()
744 eep->calTargetFbin2GHT40, in ar9380_set_txpower()
745 eep->calTargetPower2GHT40, in ar9380_set_txpower()
752 eep->calTargetFbin5G, eep->calTargetPower5G, in ar9380_set_txpower()
757 eep->calTargetFbin5GHT20, eep->calTargetPower5GHT20, in ar9380_set_txpower()
763 eep->calTargetFbin5GHT40, in ar9380_set_txpower()
764 eep->calTargetPower5GHT40, in ar9380_set_txpower()
834 const struct ar9380_eeprom *eep = sc->sc_eep; in ar9380_get_correction() local
841 pierfreq = eep->calFreqPier2G; in ar9380_get_correction()
842 pierdata = eep->calPierData2G[chain]; in ar9380_get_correction()
846 pierfreq = eep->calFreqPier5G; in ar9380_get_correction()
847 pierdata = eep->calPierData5G[chain]; in ar9380_get_correction()
865 const struct ar9380_eeprom *eep = sc->sc_eep; in ar9380_set_correction() local
872 modal = &eep->modalHeader2G; in ar9380_set_correction()
874 modal = &eep->modalHeader5G; in ar9380_set_correction()
894 eep->base_ext2.tempSlopeLow != 0) { in ar9380_set_correction()
897 5180, eep->base_ext2.tempSlopeLow, in ar9380_set_correction()
903 5785, eep->base_ext2.tempSlopeHigh); in ar9380_set_correction()